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authorVincent Lejeune <[email protected]>2012-08-01 22:49:40 +0200
committerTom Stellard <[email protected]>2012-08-15 21:07:13 +0000
commit8263408a91b6b3beb5af5de6bdc7e5d13197a268 (patch)
tree22f874d9ff229145abf992e2bfbd022bde656e20 /src/gallium/drivers/radeon/R600CodeEmitter.cpp
parent8f597d57e959830040473b548e0e04cfc63866c2 (diff)
radeon/llvm: Support for predicate bit
Tom Stellard: - A few changes to predicate register defs Signed-off-by: Tom Stellard <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeon/R600CodeEmitter.cpp')
-rw-r--r--src/gallium/drivers/radeon/R600CodeEmitter.cpp34
1 files changed, 31 insertions, 3 deletions
diff --git a/src/gallium/drivers/radeon/R600CodeEmitter.cpp b/src/gallium/drivers/radeon/R600CodeEmitter.cpp
index 870d375b6e7..02b6fdb748b 100644
--- a/src/gallium/drivers/radeon/R600CodeEmitter.cpp
+++ b/src/gallium/drivers/radeon/R600CodeEmitter.cpp
@@ -235,6 +235,8 @@ void R600CodeEmitter::EmitALUInstr(MachineInstr &MI)
{
unsigned numOperands = MI.getNumExplicitOperands();
+ if(MI.findFirstPredOperandIdx() > -1)
+ numOperands--;
// Some instructions are just place holder instructions that represent
// operations that the GPU does automatically. They should be ignored.
@@ -242,6 +244,9 @@ void R600CodeEmitter::EmitALUInstr(MachineInstr &MI)
return;
}
+ if(MI.getOpcode() == AMDGPU::PRED_X)
+ numOperands = 2;
+
// XXX Check if instruction writes a result
if (numOperands < 1) {
return;
@@ -343,7 +348,7 @@ void R600CodeEmitter::EmitSrc(const MachineOperand & MO, int chan_override)
void R600CodeEmitter::EmitDst(const MachineOperand & MO)
{
- if (MO.isReg()) {
+ if (MO.isReg() && MO.getReg() != AMDGPU::PREDICATE_BIT) {
// Emit the destination register index (1 byte)
EmitByte(getHWReg(MO.getReg()));
@@ -396,8 +401,31 @@ void R600CodeEmitter::EmitALU(MachineInstr &MI, unsigned numSrc)
EmitByte(0);
}
- // XXX: Emit predicate (1 byte)
- EmitByte(0);
+ // XXX: Emit push modifier
+ if(MI.getOperand(1).getTargetFlags() & MO_FLAG_PUSH) {
+ EmitByte(1);
+ } else {
+ EmitByte(0);
+ }
+
+ // XXX: Emit predicate (1 byte)
+ int predidx = MI.findFirstPredOperandIdx();
+ if (predidx > -1)
+ switch(MI.getOperand(predidx).getReg()) {
+ case AMDGPU::PRED_SEL_ZERO:
+ EmitByte(2);
+ break;
+ case AMDGPU::PRED_SEL_ONE:
+ EmitByte(3);
+ break;
+ default:
+ EmitByte(0);
+ break;
+ }
+ else {
+ EmitByte(0);
+ }
+
// XXX: Emit bank swizzle. (1 byte) Do we need this? It looks like
// r600_asm.c sets it.