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authorTom Stellard <[email protected]>2012-06-28 20:27:55 +0000
committerTom Stellard <[email protected]>2012-06-29 18:46:18 +0000
commita31b2f71076b9d3fe9bc5f2bae3228f1e7b99ee2 (patch)
treea1eda2beecba9682d5c9a8815ce504f13dd9c046 /src/gallium/drivers/radeon/R600CodeEmitter.cpp
parente17c586d08aee5bbaad6ac5efd2d30fe1d179406 (diff)
radeon/llvm: Enable vec4 loads on R600
Diffstat (limited to 'src/gallium/drivers/radeon/R600CodeEmitter.cpp')
-rw-r--r--src/gallium/drivers/radeon/R600CodeEmitter.cpp1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeon/R600CodeEmitter.cpp b/src/gallium/drivers/radeon/R600CodeEmitter.cpp
index 99964d4beb1..9db6ba86232 100644
--- a/src/gallium/drivers/radeon/R600CodeEmitter.cpp
+++ b/src/gallium/drivers/radeon/R600CodeEmitter.cpp
@@ -205,6 +205,7 @@ bool R600CodeEmitter::runOnMachineFunction(MachineFunction &MF) {
}
case AMDIL::VTX_READ_PARAM_eg:
case AMDIL::VTX_READ_GLOBAL_eg:
+ case AMDIL::VTX_READ_GLOBAL_128_eg:
{
uint64_t InstWord01 = getBinaryCodeForInstr(MI);
uint32_t InstWord2 = MI.getOperand(2).getImm(); // Offset