diff options
| author | Tom Stellard <[email protected]> | 2012-07-10 11:15:49 -0400 |
|---|---|---|
| committer | Tom Stellard <[email protected]> | 2012-07-11 17:47:20 +0000 |
| commit | 49ae102ee346d4be6a61ebdaba6e5d5ad8469407 (patch) | |
| tree | 069e17b22b82de1661c1f81cb1e08a80ec507d28 /src/gallium/drivers/radeon/R600CodeEmitter.cpp | |
| parent | bbdf3af8577ca61fc54c4a1615e80940c904636e (diff) | |
radeon/llvm: Use multiclasses for floating point loads
The original strategy for handling floating point loads, which was to
lower (f32 load) to (f32 bitcast (i32 load)) wasn't really working. The
main problem was that the DAG legalizer couldn't handle replacing a node
with two results (load) with a node with only one result (bitcast).
Diffstat (limited to 'src/gallium/drivers/radeon/R600CodeEmitter.cpp')
| -rw-r--r-- | src/gallium/drivers/radeon/R600CodeEmitter.cpp | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/src/gallium/drivers/radeon/R600CodeEmitter.cpp b/src/gallium/drivers/radeon/R600CodeEmitter.cpp index 4c7962bcee4..d882bb1e44a 100644 --- a/src/gallium/drivers/radeon/R600CodeEmitter.cpp +++ b/src/gallium/drivers/radeon/R600CodeEmitter.cpp @@ -203,9 +203,12 @@ bool R600CodeEmitter::runOnMachineFunction(MachineFunction &MF) { emit(inst); break; } - case AMDGPU::VTX_READ_PARAM_eg: - case AMDGPU::VTX_READ_GLOBAL_eg: - case AMDGPU::VTX_READ_GLOBAL_128_eg: + case AMDGPU::VTX_READ_PARAM_i32_eg: + case AMDGPU::VTX_READ_PARAM_f32_eg: + case AMDGPU::VTX_READ_GLOBAL_i32_eg: + case AMDGPU::VTX_READ_GLOBAL_f32_eg: + case AMDGPU::VTX_READ_GLOBAL_v4i32_eg: + case AMDGPU::VTX_READ_GLOBAL_v4f32_eg: { uint64_t InstWord01 = getBinaryCodeForInstr(MI); uint32_t InstWord2 = MI.getOperand(2).getImm(); // Offset |