radeon/llvm: Remove backend code from Mesa

This code now lives in an external tree.

For the next Mesa release fetch the code from the master branch
of this LLVM repo:
http://cgit.freedesktop.org/~tstellar/llvm/

For all subsequent Mesa releases, fetch the code from the official LLVM
project:
www.llvm.org

1 files changed, 0 insertions, 83 deletions

diff --git a/src/gallium/drivers/radeon/Makefile.sources b/src/gallium/drivers/radeon/Makefile.sources
index 5e793422d66..45d2e8f2e76 100644
--- a/src/gallium/drivers/radeon/Makefile.sources
+++ b/src/gallium/drivers/radeon/Makefile.sources
@@ -1,86 +1,3 @@
-
-TD_FILES := \
-	AMDGPU.td		\
-	AMDGPUInstrInfo.td	\
-	AMDGPUInstructions.td	\
-	AMDGPUIntrinsics.td	\
-	AMDGPURegisterInfo.td	\
-	AMDILBase.td		\
-	AMDILInstrInfo.td	\
-	AMDILIntrinsics.td	\
-	AMDILRegisterInfo.td	\
-	Processors.td		\
-	R600Instructions.td	\
-	R600Intrinsics.td	\
-	R600IntrinsicsNoOpenCL.td	\
-	R600IntrinsicsOpenCL.td	\
-	R600RegisterInfo.td	\
-	R600Schedule.td		\
-	SIInstrFormats.td	\
-	SIInstrInfo.td		\
-	SIInstructions.td	\
-	SIIntrinsics.td		\
-	SIRegisterInfo.td	\
-	SISchedule.td
-
-LLVM_GENERATED_SOURCES := \
-	R600Intrinsics.td		\
-	R600RegisterInfo.td		\
-	SIRegisterInfo.td		\
-	SIRegisterGetHWRegNum.inc		\
-	AMDGPUGenRegisterInfo.inc	\
-	AMDGPUGenInstrInfo.inc		\
-	AMDGPUGenAsmWriter.inc		\
-	AMDGPUGenDAGISel.inc		\
-	AMDGPUGenCallingConv.inc		\
-	AMDGPUGenSubtargetInfo.inc		\
-	AMDGPUGenEDInfo.inc		\
-	AMDGPUGenIntrinsics.inc		\
-	AMDGPUGenCodeEmitter.inc	\
-	AMDGPUGenMCCodeEmitter.inc	\
-	AMDGPUGenDFAPacketizer.inc
-
-LLVM_CPP_SOURCES := \
-	AMDIL7XXDevice.cpp		\
-	AMDILCFGStructurizer.cpp	\
-	AMDILDevice.cpp			\
-	AMDILDeviceInfo.cpp		\
-	AMDILEvergreenDevice.cpp	\
-	AMDILFrameLowering.cpp		\
-	AMDILIntrinsicInfo.cpp		\
-	AMDILISelDAGToDAG.cpp		\
-	AMDILISelLowering.cpp		\
-	AMDILNIDevice.cpp		\
-	AMDILPeepholeOptimizer.cpp	\
-	AMDILSIDevice.cpp		\
-	AMDGPUAsmPrinter.cpp \
-	AMDGPUMCInstLower.cpp \
-	AMDGPUSubtarget.cpp		\
-	AMDGPUTargetMachine.cpp		\
-	AMDGPUISelLowering.cpp		\
-	AMDGPUConvertToISA.cpp		\
-	AMDGPUInstrInfo.cpp		\
-	AMDGPURegisterInfo.cpp		\
-	R600ExpandSpecialInstrs.cpp	\
-	R600ISelLowering.cpp		\
-	R600InstrInfo.cpp		\
-	R600MachineFunctionInfo.cpp	\
-	R600RegisterInfo.cpp		\
-	SIAssignInterpRegs.cpp		\
-	SIInstrInfo.cpp			\
-	SIISelLowering.cpp		\
-	SILowerLiteralConstants.cpp		\
-	SILowerFlowControl.cpp	\
-	SIMachineFunctionInfo.cpp	\
-	SIRegisterInfo.cpp		\
-	InstPrinter/AMDGPUInstPrinter.cpp \
-	MCTargetDesc/AMDGPUMCAsmInfo.cpp	\
-	MCTargetDesc/AMDGPUAsmBackend.cpp \
-	MCTargetDesc/AMDGPUMCTargetDesc.cpp	\
-	MCTargetDesc/SIMCCodeEmitter.cpp \
-	MCTargetDesc/R600MCCodeEmitter.cpp \
-	TargetInfo/AMDGPUTargetInfo.cpp	\
-
 CPP_SOURCES := \
 	radeon_llvm_emit.cpp