radeon/llvm: Remove backend code from Mesa

This code now lives in an external tree.

For the next Mesa release fetch the code from the master branch
of this LLVM repo:
http://cgit.freedesktop.org/~tstellar/llvm/

For all subsequent Mesa releases, fetch the code from the official LLVM
project:
www.llvm.org

8 files changed, 0 insertions, 1450 deletions

diff --git a/src/gallium/drivers/radeon/MCTargetDesc/AMDGPUAsmBackend.cpp b/src/gallium/drivers/radeon/MCTargetDesc/AMDGPUAsmBackend.cpp
deleted file mode 100644
index 5b31bc6c8f0..00000000000
--- a/src/gallium/drivers/radeon/MCTargetDesc/AMDGPUAsmBackend.cpp
+++ /dev/null
@@ -1,80 +0,0 @@
-//===-- AMDGPUAsmBackend.cpp - AMDGPU Assembler Backend -------------------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
-#include "llvm/ADT/StringRef.h"
-#include "llvm/MC/MCAsmBackend.h"
-#include "llvm/MC/MCAssembler.h"
-#include "llvm/MC/MCObjectWriter.h"
-#include "llvm/MC/MCValue.h"
-#include "llvm/Support/TargetRegistry.h"
-
-using namespace llvm;
-
-namespace {
-
-class AMDGPUMCObjectWriter : public MCObjectWriter {
-public:
-  AMDGPUMCObjectWriter(raw_ostream &OS) : MCObjectWriter(OS, true) { }
-  virtual void ExecutePostLayoutBinding(MCAssembler &Asm,
-                                        const MCAsmLayout &Layout) {
-    //XXX: Implement if necessary.
-  }
-  virtual void RecordRelocation(const MCAssembler &Asm,
-                                const MCAsmLayout &Layout,
-                                const MCFragment *Fragment,
-                                const MCFixup &Fixup,
-                                MCValue Target, uint64_t &FixedValue) {
-    assert(!"Not implemented");
-  }
-
-  virtual void WriteObject(MCAssembler &Asm, const MCAsmLayout &Layout);
-
-};
-
-class AMDGPUAsmBackend : public MCAsmBackend {
-public:
-  AMDGPUAsmBackend(const Target &T)
-    : MCAsmBackend() {}
-
-  virtual AMDGPUMCObjectWriter *createObjectWriter(raw_ostream &OS) const;
-  virtual unsigned getNumFixupKinds() const { return 0; };
-  virtual void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
-                          uint64_t Value) const { assert(!"Not implemented"); }
-  virtual bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
-                                    const MCInstFragment *DF,
-                                    const MCAsmLayout &Layout) const {
-    return false;
-  }
-  virtual void relaxInstruction(const MCInst &Inst, MCInst &Res) const {
-    assert(!"Not implemented");
-  }
-  virtual bool mayNeedRelaxation(const MCInst &Inst) const { return false; }
-  virtual bool writeNopData(uint64_t Count, MCObjectWriter *OW) const { 
-    return true;
-  }
-};
-
-} //End anonymous namespace
-
-void AMDGPUMCObjectWriter::WriteObject(MCAssembler &Asm,
-                                       const MCAsmLayout &Layout) {
-  for (MCAssembler::iterator I = Asm.begin(), E = Asm.end(); I != E; ++I) {
-    Asm.writeSectionData(I, Layout);
-  }
-}
-
-MCAsmBackend *llvm::createAMDGPUAsmBackend(const Target &T, StringRef TT) {
-  return new AMDGPUAsmBackend(T);
-}
-
-AMDGPUMCObjectWriter * AMDGPUAsmBackend::createObjectWriter(
-                                                        raw_ostream &OS) const {
-  return new AMDGPUMCObjectWriter(OS);
-}
diff --git a/src/gallium/drivers/radeon/MCTargetDesc/AMDGPUMCAsmInfo.cpp b/src/gallium/drivers/radeon/MCTargetDesc/AMDGPUMCAsmInfo.cpp
deleted file mode 100644
index ccd5a3bfaa9..00000000000
--- a/src/gallium/drivers/radeon/MCTargetDesc/AMDGPUMCAsmInfo.cpp
+++ /dev/null
@@ -1,96 +0,0 @@
-//===-- MCTargetDesc/AMDGPUMCAsmInfo.cpp - Assembly Info ------------------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#include "AMDGPUMCAsmInfo.h"
-
-using namespace llvm;
-AMDGPUMCAsmInfo::AMDGPUMCAsmInfo(const Target &T, StringRef &TT) : MCAsmInfo()
-{
-  HasSingleParameterDotFile = false;
-  WeakDefDirective = 0;
-  //===------------------------------------------------------------------===//
-  HasSubsectionsViaSymbols = true;
-  HasMachoZeroFillDirective = false;
-  HasMachoTBSSDirective = false;
-  HasStaticCtorDtorReferenceInStaticMode = false;
-  LinkerRequiresNonEmptyDwarfLines = true;
-  MaxInstLength = 16;
-  PCSymbol = "$";
-  SeparatorString = "\n";
-  CommentColumn = 40;
-  CommentString = ";";
-  LabelSuffix = ":";
-  GlobalPrefix = "@";
-  PrivateGlobalPrefix = ";.";
-  LinkerPrivateGlobalPrefix = "!";
-  InlineAsmStart = ";#ASMSTART";
-  InlineAsmEnd = ";#ASMEND";
-  AssemblerDialect = 0;
-  AllowQuotesInName = false;
-  AllowNameToStartWithDigit = false;
-  AllowPeriodsInName = false;
-
-  //===--- Data Emission Directives -------------------------------------===//
-  ZeroDirective = ".zero";
-  AsciiDirective = ".ascii\t";
-  AscizDirective = ".asciz\t";
-  Data8bitsDirective = ".byte\t";
-  Data16bitsDirective = ".short\t";
-  Data32bitsDirective = ".long\t";
-  Data64bitsDirective = ".quad\t";
-  GPRel32Directive = 0;
-  SunStyleELFSectionSwitchSyntax = true;
-  UsesELFSectionDirectiveForBSS = true;
-  HasMicrosoftFastStdCallMangling = false;
-
-  //===--- Alignment Information ----------------------------------------===//
-  AlignDirective = ".align\t";
-  AlignmentIsInBytes = true;
-  TextAlignFillValue = 0;
-
-  //===--- Global Variable Emission Directives --------------------------===//
-  GlobalDirective = ".global";
-  ExternDirective = ".extern";
-  HasSetDirective = false;
-  HasAggressiveSymbolFolding = true;
-  LCOMMDirectiveType = LCOMM::None;
-  COMMDirectiveAlignmentIsInBytes = false;
-  HasDotTypeDotSizeDirective = false;
-  HasNoDeadStrip = true;
-  HasSymbolResolver = false;
-  WeakRefDirective = ".weakref\t";
-  LinkOnceDirective = 0;
-  //===--- Dwarf Emission Directives -----------------------------------===//
-  HasLEB128 = true;
-  SupportsDebugInformation = true;
-  ExceptionsType = ExceptionHandling::None;
-  DwarfUsesInlineInfoSection = false;
-  DwarfSectionOffsetDirective = ".offset";
-  DwarfUsesLabelOffsetForRanges = true;
-
-  //===--- CBE Asm Translation Table -----------------------------------===//
-  AsmTransCBE = 0;
-}
-const char*
-AMDGPUMCAsmInfo::getDataASDirective(unsigned int Size, unsigned int AS) const
-{
-  switch (AS) {
-    default:
-      return 0;
-    case 0:
-      return 0;
-  };
-  return 0;
-}
-
-const MCSection*
-AMDGPUMCAsmInfo::getNonexecutableStackSection(MCContext &CTX) const
-{
-  return 0;
-}
diff --git a/src/gallium/drivers/radeon/MCTargetDesc/AMDGPUMCAsmInfo.h b/src/gallium/drivers/radeon/MCTargetDesc/AMDGPUMCAsmInfo.h
deleted file mode 100644
index 0ca264beb0f..00000000000
--- a/src/gallium/drivers/radeon/MCTargetDesc/AMDGPUMCAsmInfo.h
+++ /dev/null
@@ -1,30 +0,0 @@
-//===-- MCTargetDesc/AMDGPUMCAsmInfo.h - TODO: Add brief description -------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// TODO: Add full description
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef AMDGPUMCASMINFO_H_
-#define AMDGPUMCASMINFO_H_
-
-#include "llvm/MC/MCAsmInfo.h"
-namespace llvm {
-  class Target;
-  class StringRef;
-
-  class AMDGPUMCAsmInfo : public MCAsmInfo {
-    public:
-      explicit AMDGPUMCAsmInfo(const Target &T, StringRef &TT);
-      const char*
-        getDataASDirective(unsigned int Size, unsigned int AS) const;
-      const MCSection* getNonexecutableStackSection(MCContext &CTX) const;
-  };
-} // namespace llvm
-#endif // AMDGPUMCASMINFO_H_
diff --git a/src/gallium/drivers/radeon/MCTargetDesc/AMDGPUMCCodeEmitter.h b/src/gallium/drivers/radeon/MCTargetDesc/AMDGPUMCCodeEmitter.h
deleted file mode 100644
index a75a8414e6c..00000000000
--- a/src/gallium/drivers/radeon/MCTargetDesc/AMDGPUMCCodeEmitter.h
+++ /dev/null
@@ -1,59 +0,0 @@
-//===-- AMDGPUCodeEmitter.h - AMDGPU Code Emitter interface -----------------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// CodeEmitter interface for R600 and SI codegen.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef AMDGPUCODEEMITTER_H
-#define AMDGPUCODEEMITTER_H
-
-#include "llvm/MC/MCCodeEmitter.h"
-#include "llvm/Support/raw_ostream.h"
-
-namespace llvm {
-
-  class MCInst;
-  class MCOperand;
-
-  class AMDGPUMCCodeEmitter : public MCCodeEmitter {
-  public:
-
-    uint64_t getBinaryCodeForInstr(const MCInst &MI,
-                                   SmallVectorImpl<MCFixup> &Fixups) const;
-
-    virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
-                                       SmallVectorImpl<MCFixup> &Fixups) const {
-      return 0;
-    }
-
-    virtual unsigned GPR4AlignEncode(const MCInst  &MI, unsigned OpNo,
-                                     SmallVectorImpl<MCFixup> &Fixups) const {
-      return 0;
-    }
-    virtual unsigned GPR2AlignEncode(const MCInst &MI, unsigned OpNo,
-                                     SmallVectorImpl<MCFixup> &Fixups) const {
-      return 0;
-    }
-    virtual uint64_t VOPPostEncode(const MCInst &MI, uint64_t Value) const {
-      return Value;
-    }
-    virtual uint64_t i32LiteralEncode(const MCInst &MI, unsigned OpNo,
-                                     SmallVectorImpl<MCFixup> &Fixups) const {
-      return 0;
-    }
-    virtual uint32_t SMRDmemriEncode(const MCInst &MI, unsigned OpNo,
-                                     SmallVectorImpl<MCFixup> &Fixups) const {
-      return 0;
-    }
-  };
-
-} // End namespace llvm
-
-#endif // AMDGPUCODEEMITTER_H
diff --git a/src/gallium/drivers/radeon/MCTargetDesc/AMDGPUMCTargetDesc.cpp b/src/gallium/drivers/radeon/MCTargetDesc/AMDGPUMCTargetDesc.cpp
deleted file mode 100644
index 6de20fceda6..00000000000
--- a/src/gallium/drivers/radeon/MCTargetDesc/AMDGPUMCTargetDesc.cpp
+++ /dev/null
@@ -1,111 +0,0 @@
-//===-- AMDGPUMCTargetDesc.cpp - AMDGPU Target Descriptions ---------------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file provides AMDGPU specific target descriptions.
-//
-//===----------------------------------------------------------------------===//
-
-#include "AMDGPUMCTargetDesc.h"
-#include "AMDGPUMCAsmInfo.h"
-#include "InstPrinter/AMDGPUInstPrinter.h"
-#include "llvm/MC/MachineLocation.h"
-#include "llvm/MC/MCCodeGenInfo.h"
-#include "llvm/MC/MCInstrInfo.h"
-#include "llvm/MC/MCRegisterInfo.h"
-#include "llvm/MC/MCStreamer.h"
-#include "llvm/MC/MCSubtargetInfo.h"
-#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/TargetRegistry.h"
-
-#define GET_INSTRINFO_MC_DESC
-#include "AMDGPUGenInstrInfo.inc"
-
-#define GET_SUBTARGETINFO_MC_DESC
-#include "AMDGPUGenSubtargetInfo.inc"
-
-#define GET_REGINFO_MC_DESC
-#include "AMDGPUGenRegisterInfo.inc"
-
-using namespace llvm;
-
-static MCInstrInfo *createAMDGPUMCInstrInfo() {
-  MCInstrInfo *X = new MCInstrInfo();
-  InitAMDGPUMCInstrInfo(X);
-  return X;
-}
-
-static MCRegisterInfo *createAMDGPUMCRegisterInfo(StringRef TT) {
-  MCRegisterInfo *X = new MCRegisterInfo();
-  InitAMDGPUMCRegisterInfo(X, 0);
-  return X;
-}
-
-static MCSubtargetInfo *createAMDGPUMCSubtargetInfo(StringRef TT, StringRef CPU,
-                                                   StringRef FS) {
-  MCSubtargetInfo * X = new MCSubtargetInfo();
-  InitAMDGPUMCSubtargetInfo(X, TT, CPU, FS);
-  return X;
-}
-
-static MCCodeGenInfo *createAMDGPUMCCodeGenInfo(StringRef TT, Reloc::Model RM,
-                                               CodeModel::Model CM,
-                                               CodeGenOpt::Level OL) {
-  MCCodeGenInfo *X = new MCCodeGenInfo();
-  X->InitMCCodeGenInfo(RM, CM, OL);
-  return X;
-}
-
-static MCInstPrinter *createAMDGPUMCInstPrinter(const Target &T,
-                                                unsigned SyntaxVariant,
-                                                const MCAsmInfo &MAI,
-                                                const MCInstrInfo &MII,
-                                                const MCRegisterInfo &MRI,
-                                                const MCSubtargetInfo &STI) {
-  return new AMDGPUInstPrinter(MAI, MII, MRI);
-}
-
-static MCCodeEmitter *createAMDGPUMCCodeEmitter(const MCInstrInfo &MCII,
-                                                const MCSubtargetInfo &STI,
-                                                MCContext &Ctx) {
-  if (STI.getFeatureBits() & AMDGPU::Feature64BitPtr) {
-    return createSIMCCodeEmitter(MCII, STI, Ctx);
-  } else {
-    return createR600MCCodeEmitter(MCII, STI, Ctx);
-  }
-}
-
-static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
-                                    MCContext &Ctx, MCAsmBackend &MAB,
-                                    raw_ostream &_OS,
-                                    MCCodeEmitter *_Emitter,
-                                    bool RelaxAll,
-                                    bool NoExecStack) {
-  return createPureStreamer(Ctx, MAB, _OS, _Emitter);
-}
-
-extern "C" void LLVMInitializeAMDGPUTargetMC() {
-
-  RegisterMCAsmInfo<AMDGPUMCAsmInfo> Y(TheAMDGPUTarget);
-
-  TargetRegistry::RegisterMCCodeGenInfo(TheAMDGPUTarget, createAMDGPUMCCodeGenInfo);
-
-  TargetRegistry::RegisterMCInstrInfo(TheAMDGPUTarget, createAMDGPUMCInstrInfo);
-
-  TargetRegistry::RegisterMCRegInfo(TheAMDGPUTarget, createAMDGPUMCRegisterInfo);
-
-  TargetRegistry::RegisterMCSubtargetInfo(TheAMDGPUTarget, createAMDGPUMCSubtargetInfo);
-
-  TargetRegistry::RegisterMCInstPrinter(TheAMDGPUTarget, createAMDGPUMCInstPrinter);
-
-  TargetRegistry::RegisterMCCodeEmitter(TheAMDGPUTarget, createAMDGPUMCCodeEmitter);
-
-  TargetRegistry::RegisterMCAsmBackend(TheAMDGPUTarget, createAMDGPUAsmBackend);
-
-  TargetRegistry::RegisterMCObjectStreamer(TheAMDGPUTarget, createMCStreamer);
-}
diff --git a/src/gallium/drivers/radeon/MCTargetDesc/AMDGPUMCTargetDesc.h b/src/gallium/drivers/radeon/MCTargetDesc/AMDGPUMCTargetDesc.h
deleted file mode 100644
index 328e367401a..00000000000
--- a/src/gallium/drivers/radeon/MCTargetDesc/AMDGPUMCTargetDesc.h
+++ /dev/null
@@ -1,51 +0,0 @@
-//===-- AMDGPUMCTargetDesc.h - AMDGPU Target Descriptions -----*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file provides AMDGPU specific target descriptions.
-//
-//===----------------------------------------------------------------------===//
-//
-
-#ifndef AMDGPUMCTARGETDESC_H
-#define AMDGPUMCTARGETDESC_H
-
-#include "llvm/ADT/StringRef.h"
-
-namespace llvm {
-class MCAsmBackend;
-class MCCodeEmitter;
-class MCContext;
-class MCInstrInfo;
-class MCRegisterInfo;
-class MCSubtargetInfo;
-class Target;
-
-extern Target TheAMDGPUTarget;
-
-MCCodeEmitter *createR600MCCodeEmitter(const MCInstrInfo &MCII,
-                                       const MCSubtargetInfo &STI,
-                                       MCContext &Ctx);
-
-MCCodeEmitter *createSIMCCodeEmitter(const MCInstrInfo &MCII,
-                                     const MCSubtargetInfo &STI,
-                                     MCContext &Ctx);
-
-MCAsmBackend *createAMDGPUAsmBackend(const Target &T, StringRef TT);
-} // End llvm namespace
-
-#define GET_REGINFO_ENUM
-#include "AMDGPUGenRegisterInfo.inc"
-
-#define GET_INSTRINFO_ENUM
-#include "AMDGPUGenInstrInfo.inc"
-
-#define GET_SUBTARGETINFO_ENUM
-#include "AMDGPUGenSubtargetInfo.inc"
-
-#endif // AMDGPUMCTARGETDESC_H
diff --git a/src/gallium/drivers/radeon/MCTargetDesc/R600MCCodeEmitter.cpp b/src/gallium/drivers/radeon/MCTargetDesc/R600MCCodeEmitter.cpp
deleted file mode 100644
index a11f48234cb..00000000000
--- a/src/gallium/drivers/radeon/MCTargetDesc/R600MCCodeEmitter.cpp
+++ /dev/null
@@ -1,727 +0,0 @@
-//===- R600MCCodeEmitter.cpp - Code Emitter for R600->Cayman GPU families -===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This code emitters outputs bytecode that is understood by the r600g driver
-// in the Mesa [1] project.  The bytecode is very similar to the hardware's ISA,
-// except that the size of the instruction fields are rounded up to the
-// nearest byte.
-//
-// [1] http://www.mesa3d.org/
-//
-//===----------------------------------------------------------------------===//
-
-#include "R600Defines.h"
-#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
-#include "MCTargetDesc/AMDGPUMCCodeEmitter.h"
-#include "llvm/MC/MCCodeEmitter.h"
-#include "llvm/MC/MCContext.h"
-#include "llvm/MC/MCInst.h"
-#include "llvm/MC/MCInstrInfo.h"
-#include "llvm/MC/MCRegisterInfo.h"
-#include "llvm/MC/MCSubtargetInfo.h"
-#include "llvm/Support/raw_ostream.h"
-
-#include <stdio.h>
-
-#define SRC_BYTE_COUNT 11
-#define DST_BYTE_COUNT 5
-
-using namespace llvm;
-
-namespace {
-
-class R600MCCodeEmitter : public AMDGPUMCCodeEmitter {
-  R600MCCodeEmitter(const R600MCCodeEmitter &); // DO NOT IMPLEMENT
-  void operator=(const R600MCCodeEmitter &); // DO NOT IMPLEMENT
-  const MCInstrInfo &MCII;
-  const MCSubtargetInfo &STI;
-  MCContext &Ctx;
-
-public:
-
-  R600MCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
-                    MCContext &ctx)
-    : MCII(mcii), STI(sti), Ctx(ctx) { }
-
-  /// EncodeInstruction - Encode the instruction and write it to the OS.
-  virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
-                         SmallVectorImpl<MCFixup> &Fixups) const;
-
-  /// getMachineOpValue - Reutrn the encoding for an MCOperand.
-  virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
-                                     SmallVectorImpl<MCFixup> &Fixups) const;
-private:
-
-  void EmitALUInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups,
-                    raw_ostream &OS) const;
-  void EmitSrc(const MCInst &MI, unsigned OpIdx, raw_ostream &OS) const;
-  void EmitSrcISA(const MCInst &MI, unsigned OpIdx, uint64_t &Value,
-                  raw_ostream &OS) const;
-  void EmitDst(const MCInst &MI, raw_ostream &OS) const;
-  void EmitTexInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups,
-                    raw_ostream &OS) const;
-  void EmitFCInstr(const MCInst &MI, raw_ostream &OS) const;
-
-  void EmitNullBytes(unsigned int byteCount, raw_ostream &OS) const;
-
-  void EmitByte(unsigned int byte, raw_ostream &OS) const;
-
-  void EmitTwoBytes(uint32_t bytes, raw_ostream &OS) const;
-
-  void Emit(uint32_t value, raw_ostream &OS) const;
-  void Emit(uint64_t value, raw_ostream &OS) const;
-
-  unsigned getHWRegIndex(unsigned reg) const;
-  unsigned getHWRegChan(unsigned reg) const;
-  unsigned getHWReg(unsigned regNo) const;
-
-  bool isFCOp(unsigned opcode) const;
-  bool isTexOp(unsigned opcode) const;
-  bool isFlagSet(const MCInst &MI, unsigned Operand, unsigned Flag) const;
-
-  /// getHWRegIndexGen - Get the register's hardware index.  Implemented in
-  /// R600HwRegInfo.include.
-  unsigned getHWRegIndexGen(unsigned int Reg) const;
-
-  /// getHWRegChanGen - Get the register's channel.  Implemented in
-  /// R600HwRegInfo.include.
-  unsigned getHWRegChanGen(unsigned int Reg) const;
-};
-
-} // End anonymous namespace
-
-enum RegElement {
-  ELEMENT_X = 0,
-  ELEMENT_Y,
-  ELEMENT_Z,
-  ELEMENT_W
-};
-
-enum InstrTypes {
-  INSTR_ALU = 0,
-  INSTR_TEX,
-  INSTR_FC,
-  INSTR_NATIVE,
-  INSTR_VTX
-};
-
-enum FCInstr {
-  FC_IF = 0,
-  FC_IF_INT,
-  FC_ELSE,
-  FC_ENDIF,
-  FC_BGNLOOP,
-  FC_ENDLOOP,
-  FC_BREAK,
-  FC_BREAK_NZ_INT,
-  FC_CONTINUE,
-  FC_BREAK_Z_INT,
-  FC_BREAK_NZ
-};
-
-enum TextureTypes {
-  TEXTURE_1D = 1,
-  TEXTURE_2D,
-  TEXTURE_3D,
-  TEXTURE_CUBE,
-  TEXTURE_RECT,
-  TEXTURE_SHADOW1D,
-  TEXTURE_SHADOW2D,
-  TEXTURE_SHADOWRECT,
-  TEXTURE_1D_ARRAY,
-  TEXTURE_2D_ARRAY,
-  TEXTURE_SHADOW1D_ARRAY,
-  TEXTURE_SHADOW2D_ARRAY
-};
-
-MCCodeEmitter *llvm::createR600MCCodeEmitter(const MCInstrInfo &MCII,
-                                           const MCSubtargetInfo &STI,
-                                           MCContext &Ctx) {
-  return new R600MCCodeEmitter(MCII, STI, Ctx);
-}
-
-void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
-                                       SmallVectorImpl<MCFixup> &Fixups) const {
-  if (isTexOp(MI.getOpcode())) {
-    EmitTexInstr(MI, Fixups, OS);
-  } else if (isFCOp(MI.getOpcode())){
-    EmitFCInstr(MI, OS);
-  } else if (MI.getOpcode() == AMDGPU::RETURN ||
-    MI.getOpcode() == AMDGPU::BUNDLE ||
-    MI.getOpcode() == AMDGPU::KILL) {
-    return;
-  } else {
-    switch(MI.getOpcode()) {
-    case AMDGPU::RAT_WRITE_CACHELESS_32_eg:
-    case AMDGPU::RAT_WRITE_CACHELESS_128_eg:
-      {
-        uint64_t inst = getBinaryCodeForInstr(MI, Fixups);
-        EmitByte(INSTR_NATIVE, OS);
-        Emit(inst, OS);
-        break;
-      }
-    case AMDGPU::CONSTANT_LOAD_eg:
-    case AMDGPU::VTX_READ_PARAM_i32_eg:
-    case AMDGPU::VTX_READ_PARAM_f32_eg:
-    case AMDGPU::VTX_READ_GLOBAL_i8_eg:
-    case AMDGPU::VTX_READ_GLOBAL_i32_eg:
-    case AMDGPU::VTX_READ_GLOBAL_f32_eg:
-    case AMDGPU::VTX_READ_GLOBAL_v4i32_eg:
-    case AMDGPU::VTX_READ_GLOBAL_v4f32_eg:
-      {
-        uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups);
-        uint32_t InstWord2 = MI.getOperand(2).getImm(); // Offset
-
-        EmitByte(INSTR_VTX, OS);
-        Emit(InstWord01, OS);
-        Emit(InstWord2, OS);
-        break;
-      }
-
-    default:
-      EmitALUInstr(MI, Fixups, OS);
-      break;
-    }
-  }
-}
-
-void R600MCCodeEmitter::EmitALUInstr(const MCInst &MI,
-                                     SmallVectorImpl<MCFixup> &Fixups,
-                                     raw_ostream &OS) const {
-  const MCInstrDesc &MCDesc = MCII.get(MI.getOpcode());
-  unsigned NumOperands = MI.getNumOperands();
-
-  if(MCDesc.findFirstPredOperandIdx() > -1)
-    NumOperands--;
-
-  if (GET_FLAG_OPERAND_IDX(MCDesc.TSFlags) != 0)
-    NumOperands--;
-
-  if(MI.getOpcode() == AMDGPU::PRED_X)
-    NumOperands = 2;
-
-  // XXX Check if instruction writes a result
-  if (NumOperands < 1) {
-    return;
-  }
-
-  // Emit instruction type
-  EmitByte(INSTR_ALU, OS);
-
-  uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups);
-
-  //older alu have different encoding for instructions with one or two src
-  //parameters.
-  if ((STI.getFeatureBits() & AMDGPU::FeatureR600ALUInst) &&
-      !(MCDesc.TSFlags & R600_InstFlag::OP3)) {
-    uint64_t ISAOpCode = InstWord01 & (0x3FFULL << 39);
-    InstWord01 &= ~(0x3FFULL << 39);
-    InstWord01 |= ISAOpCode << 1;
-  }
-
-  unsigned int OpIndex;
-  for (OpIndex = 1; OpIndex < NumOperands; OpIndex++) {
-    // Literal constants are always stored as the last operand.
-    if (MI.getOperand(OpIndex).isImm() || MI.getOperand(OpIndex).isFPImm()) {
-      break;
-    }
-    EmitSrcISA(MI, OpIndex, InstWord01, OS);
-  }
-
-  // Emit zeros for unused sources
-  for ( ; OpIndex < 4; OpIndex++) {
-    EmitNullBytes(SRC_BYTE_COUNT - 6, OS);
-  }
-
-  // Emit destination register
-  const MCOperand &dstOp = MI.getOperand(0);
-  if (dstOp.isReg() && dstOp.getReg() != AMDGPU::PREDICATE_BIT) {
-    //element of destination register
-    InstWord01 |= uint64_t(getHWRegChan(dstOp.getReg())) << 61;
-
-    // isClamped
-    if (isFlagSet(MI, 0, MO_FLAG_CLAMP)) {
-      InstWord01 |= 1ULL << 63;
-    }
-
-    // write mask
-    if (!isFlagSet(MI, 0, MO_FLAG_MASK) && NumOperands < 4) {
-      InstWord01 |= 1ULL << 36;
-    }
-
-    // XXX: Emit relative addressing mode
-  }
-
-  // Emit ALU
-
-  // Emit IsLast (for this instruction group) (1 byte)
-  if (!isFlagSet(MI, 0, MO_FLAG_NOT_LAST)) {
-    InstWord01 |= 1ULL << 31;
-  }
-
-  // XXX: Emit push modifier
-  if(isFlagSet(MI, 1,  MO_FLAG_PUSH)) {
-    InstWord01 |= 1ULL << 34;
-  }
-
-    // XXX: Emit predicate (1 byte)
-  int PredIdx = MCDesc.findFirstPredOperandIdx();
-  if (PredIdx != -1) {
-    switch(MI.getOperand(PredIdx).getReg()) {
-    case AMDGPU::PRED_SEL_ZERO:
-      InstWord01 |= 2ULL << 29;
-      break;
-    case AMDGPU::PRED_SEL_ONE:
-      InstWord01 |= 3ULL << 29;
-      break;
-    }
-  }
-
-  //XXX: predicate
-  //XXX: bank swizzle
-  //XXX: OMOD
-  //XXX: index mode
-
-  Emit(InstWord01, OS);
-}
-
-void R600MCCodeEmitter::EmitSrc(const MCInst &MI, unsigned OpIdx,
-                                raw_ostream &OS) const {
-  const MCOperand &MO = MI.getOperand(OpIdx);
-  union {
-    float f;
-    uint32_t i;
-  } Value;
-  Value.i = 0;
-  // Emit the source select (2 bytes).  For GPRs, this is the register index.
-  // For other potential instruction operands, (e.g. constant registers) the
-  // value of the source select is defined in the r600isa docs.
-  if (MO.isReg()) {
-    unsigned reg = MO.getReg();
-    EmitTwoBytes(getHWReg(reg), OS);
-    if (reg == AMDGPU::ALU_LITERAL_X) {
-      unsigned ImmOpIndex = MI.getNumOperands() - 1;
-      MCOperand ImmOp = MI.getOperand(ImmOpIndex);
-      if (ImmOp.isFPImm()) {
-        Value.f = ImmOp.getFPImm();
-      } else {
-        assert(ImmOp.isImm());
-        Value.i = ImmOp.getImm();
-      }
-    }
-  } else {
-    // XXX: Handle other operand types.
-    EmitTwoBytes(0, OS);
-  }
-
-  // Emit the source channel (1 byte)
-  if (MO.isReg()) {
-    EmitByte(getHWRegChan(MO.getReg()), OS);
-  } else {
-    EmitByte(0, OS);
-  }
-
-  // XXX: Emit isNegated (1 byte)
-  if ((!(isFlagSet(MI, OpIdx, MO_FLAG_ABS)))
-      && (isFlagSet(MI, OpIdx, MO_FLAG_NEG) ||
-     (MO.isReg() &&
-      (MO.getReg() == AMDGPU::NEG_ONE || MO.getReg() == AMDGPU::NEG_HALF)))){
-    EmitByte(1, OS);
-  } else {
-    EmitByte(0, OS);
-  }
-
-  // Emit isAbsolute (1 byte)
-  if (isFlagSet(MI, OpIdx, MO_FLAG_ABS)) {
-    EmitByte(1, OS);
-  } else {
-    EmitByte(0, OS);
-  }
-
-  // XXX: Emit relative addressing mode (1 byte)
-  EmitByte(0, OS);
-
-  // Emit kc_bank, This will be adjusted later by r600_asm
-  EmitByte(0, OS);
-
-  // Emit the literal value, if applicable (4 bytes).
-  Emit(Value.i, OS);
-
-}
-
-void R600MCCodeEmitter::EmitSrcISA(const MCInst &MI, unsigned OpIdx,
-                                   uint64_t &Value, raw_ostream &OS) const {
-  const MCOperand &MO = MI.getOperand(OpIdx);
-  union {
-    float f;
-    uint32_t i;
-  } InlineConstant;
-  InlineConstant.i = 0;
-  // Emit the source select (2 bytes).  For GPRs, this is the register index.
-  // For other potential instruction operands, (e.g. constant registers) the
-  // value of the source select is defined in the r600isa docs.
-  if (MO.isReg()) {
-    unsigned Reg = MO.getReg();
-    if (AMDGPUMCRegisterClasses[AMDGPU::R600_CReg32RegClassID].contains(Reg)) {
-      EmitByte(1, OS);
-    } else {
-      EmitByte(0, OS);
-    }
-
-    if (Reg == AMDGPU::ALU_LITERAL_X) {
-      unsigned ImmOpIndex = MI.getNumOperands() - 1;
-      MCOperand ImmOp = MI.getOperand(ImmOpIndex);
-      if (ImmOp.isFPImm()) {
-        InlineConstant.f = ImmOp.getFPImm();
-      } else {
-        assert(ImmOp.isImm());
-        InlineConstant.i = ImmOp.getImm();
-      }
-    }
-  } else {
-    // XXX: Handle other operand types.
-    EmitTwoBytes(0, OS);
-  }
-
-  // source channel
-  uint64_t sourceChannelValue = getHWRegChan(MO.getReg());
-  if (OpIdx == 1)
-    Value |= sourceChannelValue << 10;
-  if (OpIdx == 2)
-    Value |= sourceChannelValue << 23;
-  if (OpIdx == 3)
-    Value |= sourceChannelValue << 42;
-
-  // isNegated
-  if ((!(isFlagSet(MI, OpIdx, MO_FLAG_ABS)))
-      && (isFlagSet(MI, OpIdx, MO_FLAG_NEG) ||
-     (MO.isReg() &&
-      (MO.getReg() == AMDGPU::NEG_ONE || MO.getReg() == AMDGPU::NEG_HALF)))){
-    if (OpIdx == 1)
-      Value |= 1ULL << 12;
-    else if (OpIdx == 2)
-      Value |= 1ULL << 25;
-    else if (OpIdx == 3)
-      Value |= 1ULL << 44;
-  }
-
-  // isAbsolute
-  if (isFlagSet(MI, OpIdx, MO_FLAG_ABS)) {
-    assert(OpIdx < 3);
-    Value |= 1ULL << (32+OpIdx-1);
-  }
-
-  // XXX: relative addressing mode
-  // XXX: kc_bank
-
-  // Emit the literal value, if applicable (4 bytes).
-  Emit(InlineConstant.i, OS);
-
-}
-
-void R600MCCodeEmitter::EmitTexInstr(const MCInst &MI,
-                                     SmallVectorImpl<MCFixup> &Fixups,
-                                     raw_ostream &OS) const {
-
-  unsigned opcode = MI.getOpcode();
-  bool hasOffsets = (opcode == AMDGPU::TEX_LD);
-  unsigned op_offset = hasOffsets ? 3 : 0;
-  int64_t sampler = MI.getOperand(op_offset+2).getImm();
-  int64_t textureType = MI.getOperand(op_offset+3).getImm();
-  unsigned srcSelect[4] = {0, 1, 2, 3};
-
-  // Emit instruction type
-  EmitByte(1, OS);
-
-  // Emit instruction
-  EmitByte(getBinaryCodeForInstr(MI, Fixups), OS);
-
-  // XXX: Emit resource id r600_shader.c uses sampler + 1.  Why?
-  EmitByte(sampler + 1 + 1, OS);
-
-  // Emit source register
-  EmitByte(getHWReg(MI.getOperand(1).getReg()), OS);
-
-  // XXX: Emit src isRelativeAddress
-  EmitByte(0, OS);
-
-  // Emit destination register
-  EmitByte(getHWReg(MI.getOperand(0).getReg()), OS);
-
-  // XXX: Emit dst isRealtiveAddress
-  EmitByte(0, OS);
-
-  // XXX: Emit dst select
-  EmitByte(0, OS); // X
-  EmitByte(1, OS); // Y
-  EmitByte(2, OS); // Z
-  EmitByte(3, OS); // W
-
-  // XXX: Emit lod bias
-  EmitByte(0, OS);
-
-  // XXX: Emit coord types
-  unsigned coordType[4] = {1, 1, 1, 1};
-
-  if (textureType == TEXTURE_RECT
-      || textureType == TEXTURE_SHADOWRECT) {
-    coordType[ELEMENT_X] = 0;
-    coordType[ELEMENT_Y] = 0;
-  }
-
-  if (textureType == TEXTURE_1D_ARRAY
-      || textureType == TEXTURE_SHADOW1D_ARRAY) {
-    if (opcode == AMDGPU::TEX_SAMPLE_C_L || opcode == AMDGPU::TEX_SAMPLE_C_LB) {
-      coordType[ELEMENT_Y] = 0;
-    } else {
-      coordType[ELEMENT_Z] = 0;
-      srcSelect[ELEMENT_Z] = ELEMENT_Y;
-    }
-  } else if (textureType == TEXTURE_2D_ARRAY
-             || textureType == TEXTURE_SHADOW2D_ARRAY) {
-    coordType[ELEMENT_Z] = 0;
-  }
-
-  for (unsigned i = 0; i < 4; i++) {
-    EmitByte(coordType[i], OS);
-  }
-
-  // XXX: Emit offsets
-  if (hasOffsets)
-	  for (unsigned i = 2; i < 5; i++)
-		  EmitByte(MI.getOperand(i).getImm()<<1, OS);
-  else
-	  EmitNullBytes(3, OS);
-
-  // Emit sampler id
-  EmitByte(sampler, OS);
-
-  // XXX:Emit source select
-  if ((textureType == TEXTURE_SHADOW1D
-      || textureType == TEXTURE_SHADOW2D
-      || textureType == TEXTURE_SHADOWRECT
-      || textureType == TEXTURE_SHADOW1D_ARRAY)
-      && opcode != AMDGPU::TEX_SAMPLE_C_L
-      && opcode != AMDGPU::TEX_SAMPLE_C_LB) {
-    srcSelect[ELEMENT_W] = ELEMENT_Z;
-  }
-
-  for (unsigned i = 0; i < 4; i++) {
-    EmitByte(srcSelect[i], OS);
-  }
-}
-
-void R600MCCodeEmitter::EmitFCInstr(const MCInst &MI, raw_ostream &OS) const {
-
-  // Emit instruction type
-  EmitByte(INSTR_FC, OS);
-
-  // Emit SRC
-  unsigned NumOperands = MI.getNumOperands();
-  if (NumOperands > 0) {
-    assert(NumOperands == 1);
-    EmitSrc(MI, 0, OS);
-  } else {
-    EmitNullBytes(SRC_BYTE_COUNT, OS);
-  }
-
-  // Emit FC Instruction
-  enum FCInstr instr;
-  switch (MI.getOpcode()) {
-  case AMDGPU::BREAK_LOGICALZ_f32:
-    instr = FC_BREAK;
-    break;
-  case AMDGPU::BREAK_LOGICALNZ_f32:
-    instr = FC_BREAK_NZ;
-    break;
-  case AMDGPU::BREAK_LOGICALNZ_i32:
-    instr = FC_BREAK_NZ_INT;
-    break;
-  case AMDGPU::BREAK_LOGICALZ_i32:
-    instr = FC_BREAK_Z_INT;
-    break;
-  case AMDGPU::CONTINUE_LOGICALNZ_f32:
-  case AMDGPU::CONTINUE_LOGICALNZ_i32:
-    instr = FC_CONTINUE;
-    break;
-  case AMDGPU::IF_LOGICALNZ_f32:
-    instr = FC_IF;
-  case AMDGPU::IF_LOGICALNZ_i32:
-    instr = FC_IF_INT;
-    break;
-  case AMDGPU::IF_LOGICALZ_f32:
-    abort();
-    break;
-  case AMDGPU::ELSE:
-    instr = FC_ELSE;
-    break;
-  case AMDGPU::ENDIF:
-    instr = FC_ENDIF;
-    break;
-  case AMDGPU::ENDLOOP:
-    instr = FC_ENDLOOP;
-    break;
-  case AMDGPU::WHILELOOP:
-    instr = FC_BGNLOOP;
-    break;
-  default:
-    abort();
-    break;
-  }
-  EmitByte(instr, OS);
-}
-
-void R600MCCodeEmitter::EmitNullBytes(unsigned int ByteCount,
-                                      raw_ostream &OS) const {
-
-  for (unsigned int i = 0; i < ByteCount; i++) {
-    EmitByte(0, OS);
-  }
-}
-
-void R600MCCodeEmitter::EmitByte(unsigned int Byte, raw_ostream &OS) const {
-  OS.write((uint8_t) Byte & 0xff);
-}
-
-void R600MCCodeEmitter::EmitTwoBytes(unsigned int Bytes,
-                                     raw_ostream &OS) const {
-  OS.write((uint8_t) (Bytes & 0xff));
-  OS.write((uint8_t) ((Bytes >> 8) & 0xff));
-}
-
-void R600MCCodeEmitter::Emit(uint32_t Value, raw_ostream &OS) const {
-  for (unsigned i = 0; i < 4; i++) {
-    OS.write((uint8_t) ((Value >> (8 * i)) & 0xff));
-  }
-}
-
-void R600MCCodeEmitter::Emit(uint64_t Value, raw_ostream &OS) const {
-  for (unsigned i = 0; i < 8; i++) {
-    EmitByte((Value >> (8 * i)) & 0xff, OS);
-  }
-}
-
-unsigned R600MCCodeEmitter::getHWRegIndex(unsigned reg) const {
-  switch(reg) {
-  case AMDGPU::ZERO: return 248;
-  case AMDGPU::ONE:
-  case AMDGPU::NEG_ONE: return 249;
-  case AMDGPU::ONE_INT: return 250;
-  case AMDGPU::HALF:
-  case AMDGPU::NEG_HALF: return 252;
-  case AMDGPU::ALU_LITERAL_X: return 253;
-  case AMDGPU::PREDICATE_BIT:
-  case AMDGPU::PRED_SEL_OFF:
-  case AMDGPU::PRED_SEL_ZERO:
-  case AMDGPU::PRED_SEL_ONE:
-    return 0;
-  default: return getHWRegIndexGen(reg);
-  }
-}
-
-unsigned R600MCCodeEmitter::getHWRegChan(unsigned reg) const {
-  switch(reg) {
-  case AMDGPU::ZERO:
-  case AMDGPU::ONE:
-  case AMDGPU::ONE_INT:
-  case AMDGPU::NEG_ONE:
-  case AMDGPU::HALF:
-  case AMDGPU::NEG_HALF:
-  case AMDGPU::ALU_LITERAL_X:
-  case AMDGPU::PREDICATE_BIT:
-  case AMDGPU::PRED_SEL_OFF:
-  case AMDGPU::PRED_SEL_ZERO:
-  case AMDGPU::PRED_SEL_ONE:
-    return 0;
-  default: return getHWRegChanGen(reg);
-  }
-}
-unsigned R600MCCodeEmitter::getHWReg(unsigned RegNo) const {
-  unsigned HWReg;
-
-  HWReg = getHWRegIndex(RegNo);
-  if (AMDGPUMCRegisterClasses[AMDGPU::R600_CReg32RegClassID].contains(RegNo)) {
-    HWReg += 512;
-  }
-  return HWReg;
-}
-
-uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI,
-                                              const MCOperand &MO,
-                                        SmallVectorImpl<MCFixup> &Fixup) const {
-  if (MO.isReg()) {
-    return getHWRegIndex(MO.getReg());
-  } else if (MO.isImm()) {
-    return MO.getImm();
-  } else {
-    assert(0);
-    return 0;
-  }
-}
-
-//===----------------------------------------------------------------------===//
-// Encoding helper functions
-//===----------------------------------------------------------------------===//
-
-bool R600MCCodeEmitter::isFCOp(unsigned opcode) const {
-  switch(opcode) {
-  default: return false;
-  case AMDGPU::BREAK_LOGICALZ_f32:
-  case AMDGPU::BREAK_LOGICALNZ_i32:
-  case AMDGPU::BREAK_LOGICALZ_i32:
-  case AMDGPU::BREAK_LOGICALNZ_f32:
-  case AMDGPU::CONTINUE_LOGICALNZ_f32:
-  case AMDGPU::IF_LOGICALNZ_i32:
-  case AMDGPU::IF_LOGICALZ_f32:
-  case AMDGPU::ELSE:
-  case AMDGPU::ENDIF:
-  case AMDGPU::ENDLOOP:
-  case AMDGPU::IF_LOGICALNZ_f32:
-  case AMDGPU::WHILELOOP:
-    return true;
-  }
-}
-
-bool R600MCCodeEmitter::isTexOp(unsigned opcode) const {
-  switch(opcode) {
-  default: return false;
-  case AMDGPU::TEX_LD:
-  case AMDGPU::TEX_GET_TEXTURE_RESINFO:
-  case AMDGPU::TEX_SAMPLE:
-  case AMDGPU::TEX_SAMPLE_C:
-  case AMDGPU::TEX_SAMPLE_L:
-  case AMDGPU::TEX_SAMPLE_C_L:
-  case AMDGPU::TEX_SAMPLE_LB:
-  case AMDGPU::TEX_SAMPLE_C_LB:
-  case AMDGPU::TEX_SAMPLE_G:
-  case AMDGPU::TEX_SAMPLE_C_G:
-  case AMDGPU::TEX_GET_GRADIENTS_H:
-  case AMDGPU::TEX_GET_GRADIENTS_V:
-  case AMDGPU::TEX_SET_GRADIENTS_H:
-  case AMDGPU::TEX_SET_GRADIENTS_V:
-    return true;
-  }
-}
-
-bool R600MCCodeEmitter::isFlagSet(const MCInst &MI, unsigned Operand,
-                                  unsigned Flag) const {
-  const MCInstrDesc &MCDesc = MCII.get(MI.getOpcode());
-  unsigned FlagIndex = GET_FLAG_OPERAND_IDX(MCDesc.TSFlags);
-  if (FlagIndex == 0) {
-    return false;
-  }
-  assert(MI.getOperand(FlagIndex).isImm());
-  return !!((MI.getOperand(FlagIndex).getImm() >>
-            (NUM_MO_FLAGS * Operand)) & Flag);
-}
-#define R600RegisterInfo R600MCCodeEmitter
-#include "R600HwRegInfo.include"
-#undef R600RegisterInfo
-
-#include "AMDGPUGenMCCodeEmitter.inc"
diff --git a/src/gallium/drivers/radeon/MCTargetDesc/SIMCCodeEmitter.cpp b/src/gallium/drivers/radeon/MCTargetDesc/SIMCCodeEmitter.cpp
deleted file mode 100644
index ca4b579dcce..00000000000
--- a/src/gallium/drivers/radeon/MCTargetDesc/SIMCCodeEmitter.cpp
+++ /dev/null
@@ -1,296 +0,0 @@
-//===-- SIMCCodeEmitter.cpp - SI Code Emitter -------------------------------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// The SI code emitter produces machine code that can be executed directly on
-// the GPU device.
-//
-//===----------------------------------------------------------------------===//
-
-#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
-#include "MCTargetDesc/AMDGPUMCCodeEmitter.h"
-#include "llvm/MC/MCCodeEmitter.h"
-#include "llvm/MC/MCContext.h"
-#include "llvm/MC/MCInst.h"
-#include "llvm/MC/MCInstrInfo.h"
-#include "llvm/MC/MCRegisterInfo.h"
-#include "llvm/MC/MCSubtargetInfo.h"
-#include "llvm/Support/raw_ostream.h"
-
-#define VGPR_BIT(src_idx) (1ULL << (9 * src_idx - 1))
-#define SI_INSTR_FLAGS_ENCODING_MASK 0xf
-
-// These must be kept in sync with SIInstructions.td and also the
-// InstrEncodingInfo array in SIInstrInfo.cpp.
-//
-// NOTE: This enum is only used to identify the encoding type within LLVM,
-// the actual encoding type that is part of the instruction format is different
-namespace SIInstrEncodingType {
-  enum Encoding {
-    EXP = 0,
-    LDS = 1,
-    MIMG = 2,
-    MTBUF = 3,
-    MUBUF = 4,
-    SMRD = 5,
-    SOP1 = 6,
-    SOP2 = 7,
-    SOPC = 8,
-    SOPK = 9,
-    SOPP = 10,
-    VINTRP = 11,
-    VOP1 = 12,
-    VOP2 = 13,
-    VOP3 = 14,
-    VOPC = 15
-  };
-}
-
-using namespace llvm;
-
-namespace {
-class SIMCCodeEmitter : public  AMDGPUMCCodeEmitter {
-  SIMCCodeEmitter(const SIMCCodeEmitter &); // DO NOT IMPLEMENT
-  void operator=(const SIMCCodeEmitter &); // DO NOT IMPLEMENT
-  const MCInstrInfo &MCII;
-  const MCSubtargetInfo &STI;
-  MCContext &Ctx;
-
-public:
-  SIMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
-                  MCContext &ctx)
-    : MCII(mcii), STI(sti), Ctx(ctx) { }
-
-  ~SIMCCodeEmitter() { }
-
-  /// EncodeInstruction - Encode the instruction and write it to the OS.
-  virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
-                         SmallVectorImpl<MCFixup> &Fixups) const;
-
-  /// getMachineOpValue - Reutrn the encoding for an MCOperand.
-  virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
-                                     SmallVectorImpl<MCFixup> &Fixups) const;
-
-public:
-
-  /// GPRAlign - Encode a sequence of registers with the correct alignment.
-  unsigned GPRAlign(const MCInst &MI, unsigned OpNo, unsigned shift) const;
-
-  /// GPR2AlignEncode - Encoding for when 2 consecutive registers are used
-  virtual unsigned GPR2AlignEncode(const MCInst &MI, unsigned OpNo,
-                                   SmallVectorImpl<MCFixup> &Fixup) const;
-
-  /// GPR4AlignEncode - Encoding for when 4 consectuive registers are used 
-  virtual unsigned GPR4AlignEncode(const MCInst &MI, unsigned OpNo,
-                                   SmallVectorImpl<MCFixup> &Fixup) const;
-
-  /// SMRDmemriEncode - Encoding for SMRD indexed loads
-  virtual uint32_t SMRDmemriEncode(const MCInst &MI, unsigned OpNo,
-                                   SmallVectorImpl<MCFixup> &Fixup) const;
-
-  /// VOPPostEncode - Post-Encoder method for VOP instructions 
-  virtual uint64_t VOPPostEncode(const MCInst &MI, uint64_t Value) const;
-
-private:
-
-  ///getEncodingType =  Return this SIInstrEncodingType for this instruction.
-  unsigned getEncodingType(const MCInst &MI) const;
-
-  ///getEncodingBytes - Get then size in bytes of this instructions encoding.
-  unsigned getEncodingBytes(const MCInst &MI) const;
-
-  /// getRegBinaryCode - Returns the hardware encoding for a register
-  unsigned getRegBinaryCode(unsigned reg) const;
-
-  /// getHWRegNum - Generated function that returns the hardware encoding for
-  /// a register
-  unsigned getHWRegNum(unsigned reg) const;
-
-};
-
-} // End anonymous namespace
-
-MCCodeEmitter *llvm::createSIMCCodeEmitter(const MCInstrInfo &MCII,
-                                           const MCSubtargetInfo &STI,
-                                           MCContext &Ctx) {
-  return new SIMCCodeEmitter(MCII, STI, Ctx);
-}
-
-void SIMCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
-                                       SmallVectorImpl<MCFixup> &Fixups) const {
-  uint64_t Encoding = getBinaryCodeForInstr(MI, Fixups);
-  unsigned bytes = getEncodingBytes(MI);
-  for (unsigned i = 0; i < bytes; i++) {
-    OS.write((uint8_t) ((Encoding >> (8 * i)) & 0xff));
-  }
-}
-
-uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI,
-                                            const MCOperand &MO,
-                                       SmallVectorImpl<MCFixup> &Fixups) const {
-  if (MO.isReg()) {
-    return getRegBinaryCode(MO.getReg());
-  } else if (MO.isImm()) {
-    return MO.getImm();
-  } else if (MO.isFPImm()) {
-    // XXX: Not all instructions can use inline literals
-    // XXX: We should make sure this is a 32-bit constant
-    union {
-      float F;
-      uint32_t I;
-    } Imm;
-    Imm.F = MO.getFPImm();
-    return Imm.I;
-  } else{
-    llvm_unreachable("Encoding of this operand type is not supported yet.");
-  }
-  return 0;
-}
-
-//===----------------------------------------------------------------------===//
-// Custom Operand Encodings
-//===----------------------------------------------------------------------===//
-
-unsigned SIMCCodeEmitter::GPRAlign(const MCInst &MI, unsigned OpNo,
-                                   unsigned shift) const {
-  unsigned regCode = getRegBinaryCode(MI.getOperand(OpNo).getReg());
-  return regCode >> shift;
-  return 0;
-}
-unsigned SIMCCodeEmitter::GPR2AlignEncode(const MCInst &MI,
-                                          unsigned OpNo ,
-                                        SmallVectorImpl<MCFixup> &Fixup) const {
-  return GPRAlign(MI, OpNo, 1);
-}
-
-unsigned SIMCCodeEmitter::GPR4AlignEncode(const MCInst &MI,
-                                          unsigned OpNo,
-                                        SmallVectorImpl<MCFixup> &Fixup) const {
-  return GPRAlign(MI, OpNo, 2);
-}
-
-#define SMRD_OFFSET_MASK 0xff
-#define SMRD_IMM_SHIFT 8
-#define SMRD_SBASE_MASK 0x3f
-#define SMRD_SBASE_SHIFT 9
-/// SMRDmemriEncode - This function is responsibe for encoding the offset
-/// and the base ptr for SMRD instructions it should return a bit string in
-/// this format:
-///
-/// OFFSET = bits{7-0}
-/// IMM    = bits{8}
-/// SBASE  = bits{14-9}
-///
-uint32_t SIMCCodeEmitter::SMRDmemriEncode(const MCInst &MI, unsigned OpNo,
-                                        SmallVectorImpl<MCFixup> &Fixup) const {
-  uint32_t Encoding;
-
-  const MCOperand &OffsetOp = MI.getOperand(OpNo + 1);
-
-  //XXX: Use this function for SMRD loads with register offsets
-  assert(OffsetOp.isImm());
-
-  Encoding =
-      (getMachineOpValue(MI, OffsetOp, Fixup) & SMRD_OFFSET_MASK)
-    | (1 << SMRD_IMM_SHIFT) //XXX If the Offset is a register we shouldn't set this bit
-    | ((GPR2AlignEncode(MI, OpNo, Fixup) & SMRD_SBASE_MASK) << SMRD_SBASE_SHIFT)
-    ;
-
-  return Encoding;
-}
-
-//===----------------------------------------------------------------------===//
-// Post Encoder Callbacks
-//===----------------------------------------------------------------------===//
-
-uint64_t SIMCCodeEmitter::VOPPostEncode(const MCInst &MI, uint64_t Value) const{
-  unsigned encodingType = getEncodingType(MI);
-  unsigned numSrcOps;
-  unsigned vgprBitOffset;
-
-  if (encodingType == SIInstrEncodingType::VOP3) {
-    numSrcOps = 3;
-    vgprBitOffset = 32;
-  } else {
-    numSrcOps = 1;
-    vgprBitOffset = 0;
-  }
-
-  // Add one to skip over the destination reg operand.
-  for (unsigned opIdx = 1; opIdx < numSrcOps + 1; opIdx++) {
-    const MCOperand &MO = MI.getOperand(opIdx);
-    if (MO.isReg()) {
-      unsigned reg = MI.getOperand(opIdx).getReg();
-      if (AMDGPUMCRegisterClasses[AMDGPU::VReg_32RegClassID].contains(reg) ||
-          AMDGPUMCRegisterClasses[AMDGPU::VReg_64RegClassID].contains(reg)) {
-        Value |= (VGPR_BIT(opIdx)) << vgprBitOffset;
-      }
-    } else if (MO.isFPImm()) {
-      union {
-        float f;
-        uint32_t i;
-      } Imm;
-      // XXX: Not all instructions can use inline literals
-      // XXX: We should make sure this is a 32-bit constant
-      Imm.f = MO.getFPImm();
-      Value |= ((uint64_t)Imm.i) << 32;
-    }
-  }
-  return Value;
-}
-
-//===----------------------------------------------------------------------===//
-// Encoding helper functions
-//===----------------------------------------------------------------------===//
-
-unsigned SIMCCodeEmitter::getEncodingType(const MCInst &MI) const {
-  return MCII.get(MI.getOpcode()).TSFlags & SI_INSTR_FLAGS_ENCODING_MASK;
-}
-
-unsigned SIMCCodeEmitter::getEncodingBytes(const MCInst &MI) const {
-
-  // These instructions aren't real instructions with an encoding type, so
-  // we need to manually specify their size.
-  switch (MI.getOpcode()) {
-  default: break;
-  case AMDGPU::SI_LOAD_LITERAL_I32:
-  case AMDGPU::SI_LOAD_LITERAL_F32:
-    return 4;
-  }
-
-  unsigned encoding_type = getEncodingType(MI);
-  switch (encoding_type) {
-    case SIInstrEncodingType::EXP:
-    case SIInstrEncodingType::LDS:
-    case SIInstrEncodingType::MUBUF:
-    case SIInstrEncodingType::MTBUF:
-    case SIInstrEncodingType::MIMG:
-    case SIInstrEncodingType::VOP3:
-      return 8;
-    default:
-      return 4;
-  }
-}
-
-
-unsigned SIMCCodeEmitter::getRegBinaryCode(unsigned reg) const {
-  switch (reg) {
-    case AMDGPU::VCC: return 106;
-    case AMDGPU::M0: return 124;
-    case AMDGPU::EXEC: return 126;
-    case AMDGPU::EXEC_LO: return 126;
-    case AMDGPU::EXEC_HI: return 127;
-    case AMDGPU::SREG_LIT_0: return 128;
-    case AMDGPU::SI_LITERAL_CONSTANT: return 255;
-    default: return getHWRegNum(reg);
-  }
-}
-
-#define SIRegisterInfo SIMCCodeEmitter
-#include "SIRegisterGetHWRegNum.inc"
-#undef SIRegisterInfo