radeon/llvm: Merge AMDILSubtarget into AMDGPUSubtarget

1 files changed, 3 insertions, 3 deletions

diff --git a/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp b/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp
index 7b199f17028..f2672ca6e8d 100644
--- a/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp
+++ b/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp
@@ -78,7 +78,7 @@ bool AMDGPUTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
                                                      DisableVerify);
   assert(fail);
 
-  const AMDILSubtarget &STM = getSubtarget<AMDILSubtarget>();
+  const AMDGPUSubtarget &STM = getSubtarget<AMDGPUSubtarget>();
   std::string gpu = STM.getDeviceName();
   if (gpu == "SI") {
     PM.add(createSICodeEmitterPass(Out));
@@ -119,7 +119,7 @@ TargetPassConfig *AMDGPUTargetMachine::createPassConfig(PassManagerBase &PM) {
 bool
 AMDGPUPassConfig::addPreISel()
 {
-  const AMDILSubtarget &ST = TM->getSubtarget<AMDILSubtarget>();
+  const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
   if (ST.device()->getGeneration() <= AMDILDeviceInfo::HD6XXX) {
     PM->add(createR600KernelParametersPass(
                      getAMDGPUTargetMachine().getTargetData()));
@@ -134,7 +134,7 @@ bool AMDGPUPassConfig::addInstSelector() {
 }
 
 bool AMDGPUPassConfig::addPreRegAlloc() {
-  const AMDILSubtarget &ST = TM->getSubtarget<AMDILSubtarget>();
+  const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
 
   if (ST.device()->getGeneration() > AMDILDeviceInfo::HD6XXX) {
     PM->add(createSIAssignInterpRegsPass(*TM));