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authorTom Stellard <[email protected]>2012-05-08 13:08:29 -0400
committerTom Stellard <[email protected]>2012-05-08 15:47:46 -0400
commita8d82c44f79e27d2b78458f9ea560c73eef3d3b5 (patch)
tree8ccab60297b2cb83e80eba498a0e048a325311f7 /src/gallium/drivers/radeon/AMDGPUIntrinsics.td
parent8a4c25dd7e9002ab7a2821753bcae1ff6af2ca1c (diff)
radeon/llvm: Remove the EXPORT_REG instruction
Diffstat (limited to 'src/gallium/drivers/radeon/AMDGPUIntrinsics.td')
-rw-r--r--src/gallium/drivers/radeon/AMDGPUIntrinsics.td3
1 files changed, 1 insertions, 2 deletions
diff --git a/src/gallium/drivers/radeon/AMDGPUIntrinsics.td b/src/gallium/drivers/radeon/AMDGPUIntrinsics.td
index 09bddb58e17..b2aeaee4121 100644
--- a/src/gallium/drivers/radeon/AMDGPUIntrinsics.td
+++ b/src/gallium/drivers/radeon/AMDGPUIntrinsics.td
@@ -13,11 +13,10 @@
let TargetPrefix = "AMDGPU", isTarget = 1 in {
- def int_AMDGPU_export_reg : Intrinsic<[], [llvm_float_ty], []>;
def int_AMDGPU_load_const : Intrinsic<[llvm_float_ty], [llvm_i32_ty], []>;
def int_AMDGPU_load_imm : Intrinsic<[llvm_v4f32_ty], [llvm_i32_ty], []>;
def int_AMDGPU_reserve_reg : Intrinsic<[], [llvm_i32_ty], []>;
- def int_AMDGPU_store_output : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_i32_ty], []>;
+ def int_AMDGPU_store_output : Intrinsic<[], [llvm_float_ty, llvm_i32_ty], []>;
def int_AMDGPU_swizzle : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty], []>;
def int_AMDGPU_arl : Intrinsic<[llvm_i32_ty], [llvm_float_ty], []>;