diff options
| author | Vadim Girlin <[email protected]> | 2012-05-07 13:06:22 +0400 |
|---|---|---|
| committer | Vadim Girlin <[email protected]> | 2012-05-08 01:18:23 +0400 |
| commit | 996fa375ec275ab5053855dc95f9cc4f301d596c (patch) | |
| tree | 8bcecb5a08dd1add1c1ab85492ba8a19bf2f46fc /src/gallium/drivers/radeon/AMDGPUIntrinsics.td | |
| parent | e9be193430a9c50975bc2ce4724e5cc517502467 (diff) | |
radeon/llvm: add support for some ALU instructions
Add support for IABS, NOT, AND, XOR, OR, UADD, UDIV, IDIV, MOD, UMOD, INEG,
I2F, U2F, F2U, F2I, USEQ, USGE, USLT, USNE, ISGE, ISLT, ROUND, MIN, MAX,
IMIN, IMAX, UMIN, UMAX
Signed-off-by: Vadim Girlin <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeon/AMDGPUIntrinsics.td')
| -rw-r--r-- | src/gallium/drivers/radeon/AMDGPUIntrinsics.td | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeon/AMDGPUIntrinsics.td b/src/gallium/drivers/radeon/AMDGPUIntrinsics.td index 41f9ca21bcd..d8ea45287a4 100644 --- a/src/gallium/drivers/radeon/AMDGPUIntrinsics.td +++ b/src/gallium/drivers/radeon/AMDGPUIntrinsics.td @@ -35,7 +35,7 @@ let TargetPrefix = "AMDGPU", isTarget = 1 in { def int_AMDGPU_rsq : Intrinsic<[llvm_float_ty], [llvm_float_ty], []>; def int_AMDGPU_seq : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], []>; def int_AMDGPU_sgt : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], []>; - def int_AMDGPU_sge : BinaryIntFloat; + def int_AMDGPU_sge : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], []>; def int_AMDGPU_sin : Intrinsic<[llvm_float_ty], [llvm_float_ty], []>; def int_AMDGPU_sle : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], []>; def int_AMDGPU_sne : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], []>; @@ -50,6 +50,10 @@ let TargetPrefix = "AMDGPU", isTarget = 1 in { def int_AMDGPU_trunc : Intrinsic<[llvm_float_ty], [llvm_float_ty], []>; def int_AMDGPU_ddx : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], []>; def int_AMDGPU_ddy : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], []>; + def int_AMDGPU_imax : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>; + def int_AMDGPU_imin : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>; + def int_AMDGPU_umax : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>; + def int_AMDGPU_umin : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>; } let TargetPrefix = "TGSI", isTarget = 1 in { |