diff options
| author | Tom Stellard <[email protected]> | 2012-05-07 15:20:26 -0400 |
|---|---|---|
| committer | Tom Stellard <[email protected]> | 2012-05-08 15:47:45 -0400 |
| commit | 52a7f212d36bd9829494bd588ecb9a3ebe9fc28a (patch) | |
| tree | 6c4bb5a2d57b80d7d8b082edfd0ae7b72e9107b6 /src/gallium/drivers/radeon/AMDGPUInstructions.td | |
| parent | e042b3aeed917b179d24c1f7a099c4cce56d2e25 (diff) | |
radeon/llvm: Remove the ReorderPreloadInstructions pass
Diffstat (limited to 'src/gallium/drivers/radeon/AMDGPUInstructions.td')
| -rw-r--r-- | src/gallium/drivers/radeon/AMDGPUInstructions.td | 11 |
1 files changed, 3 insertions, 8 deletions
diff --git a/src/gallium/drivers/radeon/AMDGPUInstructions.td b/src/gallium/drivers/radeon/AMDGPUInstructions.td index 0433c8dcd95..f5b87f3333a 100644 --- a/src/gallium/drivers/radeon/AMDGPUInstructions.td +++ b/src/gallium/drivers/radeon/AMDGPUInstructions.td @@ -16,14 +16,12 @@ include "AMDGPUInstrEnums.td" class AMDGPUInst <dag outs, dag ins, string asm, list<dag> pattern> : Instruction { field bits<16> AMDILOp = 0; field bits<3> Gen = 0; - field bit PreloadReg = 0; let Namespace = "AMDIL"; let OutOperandList = outs; let InOperandList = ins; let AsmString = asm; let Pattern = pattern; - let TSFlags{32} = PreloadReg; let TSFlags{42-40} = Gen; let TSFlags{63-48} = AMDILOp; } @@ -48,9 +46,7 @@ let isCodeGenOnly = 1 in { (outs GPRF32:$dst), (ins i32imm:$src), "LOAD_INPUT $dst, $src", - [] >{ - let PreloadReg = 1; - } + [] >; def MASK_WRITE : AMDGPUShaderInst < (outs), @@ -63,9 +59,8 @@ let isCodeGenOnly = 1 in { (outs GPRF32:$dst), (ins i32imm:$src), "RESERVE_REG $dst, $src", - [(set GPRF32:$dst, (int_AMDGPU_reserve_reg imm:$src))]> { - let PreloadReg = 1; - } + [(set GPRF32:$dst, (int_AMDGPU_reserve_reg imm:$src))] + >; def STORE_OUTPUT: AMDGPUShaderInst < (outs GPRF32:$dst), |