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authorTom Stellard <[email protected]>2012-05-11 13:44:24 -0400
committerTom Stellard <[email protected]>2012-05-11 15:09:52 -0400
commitbcfc97dbf40c256ed59c2424e0c55b845f0f2569 (patch)
tree75f46800f74716e7703c47a8f0b5b04a1551be6a /src/gallium/drivers/radeon/AMDGPUInstrInfo.h
parent23c0d469e55b3cb79ad4b2fd0d961562a26234fd (diff)
radeon/llvm: More comments and cleanups
Diffstat (limited to 'src/gallium/drivers/radeon/AMDGPUInstrInfo.h')
-rw-r--r--src/gallium/drivers/radeon/AMDGPUInstrInfo.h6
1 files changed, 5 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeon/AMDGPUInstrInfo.h b/src/gallium/drivers/radeon/AMDGPUInstrInfo.h
index 930b41e7191..0f3698930a9 100644
--- a/src/gallium/drivers/radeon/AMDGPUInstrInfo.h
+++ b/src/gallium/drivers/radeon/AMDGPUInstrInfo.h
@@ -7,7 +7,7 @@
//
//===----------------------------------------------------------------------===//
//
-// This file contains the definitoin of a TargetInstrInfo class that is common
+// This file contains the definition of a TargetInstrInfo class that is common
// to all AMD GPUs.
//
//===----------------------------------------------------------------------===//
@@ -37,8 +37,12 @@ public:
virtual const AMDGPURegisterInfo &getRegisterInfo() const = 0;
+ /// getISAOpcode - This function takes an AMDIL opcode as an argument and
+ /// returns an equivalent ISA opcode.
virtual unsigned getISAOpcode(unsigned AMDILopcode) const;
+ /// convertToISA - Convert the AMDIL MachineInstr to a supported ISA
+ /// MachineInstr
virtual MachineInstr * convertToISA(MachineInstr & MI, MachineFunction &MF,
DebugLoc DL) const;