summaryrefslogtreecommitdiffstats
path: root/src/gallium/drivers/radeon/AMDGPUInstrInfo.cpp
diff options
context:
space:
mode:
authorTom Stellard <[email protected]>2012-06-05 20:10:31 -0400
committerTom Stellard <[email protected]>2012-06-06 13:46:04 -0400
commitd4942eb9fa1247053619be2b1e5a1b79f35c535d (patch)
treedbc234aba08f848d97a4be6b7b680df932fd486b /src/gallium/drivers/radeon/AMDGPUInstrInfo.cpp
parentedceed1b9a46c4a92a6113e8b1c5d2433568143d (diff)
radeon/llvm: Remove obselete hooks for the ConvertToISA pass
We can't remove this pass yet, because we need it to convert AMDIL registers in BRANCH* instructions, but we don't need it for instruction conversion any more.
Diffstat (limited to 'src/gallium/drivers/radeon/AMDGPUInstrInfo.cpp')
-rw-r--r--src/gallium/drivers/radeon/AMDGPUInstrInfo.cpp3
1 files changed, 1 insertions, 2 deletions
diff --git a/src/gallium/drivers/radeon/AMDGPUInstrInfo.cpp b/src/gallium/drivers/radeon/AMDGPUInstrInfo.cpp
index 3c94c3da817..d2bb4e16b47 100644
--- a/src/gallium/drivers/radeon/AMDGPUInstrInfo.cpp
+++ b/src/gallium/drivers/radeon/AMDGPUInstrInfo.cpp
@@ -29,10 +29,9 @@ MachineInstr * AMDGPUInstrInfo::convertToISA(MachineInstr & MI, MachineFunction
MachineInstrBuilder newInstr;
MachineRegisterInfo &MRI = MF.getRegInfo();
const AMDGPURegisterInfo & RI = getRegisterInfo();
- unsigned ISAOpcode = getISAOpcode(MI.getOpcode());
// Create the new instruction
- newInstr = BuildMI(MF, DL, TM.getInstrInfo()->get(ISAOpcode));
+ newInstr = BuildMI(MF, DL, TM.getInstrInfo()->get(MI.getOpcode()));
for (unsigned i = 0; i < MI.getNumOperands(); i++) {
MachineOperand &MO = MI.getOperand(i);