diff options
author | Tom Stellard <[email protected]> | 2012-07-27 20:06:43 +0000 |
---|---|---|
committer | Tom Stellard <[email protected]> | 2012-07-30 21:10:08 +0000 |
commit | 0ce6e506016222b264163ee718202371f19064db (patch) | |
tree | ff0ca7a87a3e91e8145f5a153edcbbbf08dcf081 /src/gallium/drivers/radeon/AMDGPUInstrInfo.cpp | |
parent | caeaf43dad367a9a39d2f42d91731148f6dfdf32 (diff) |
radeon/llvm: Remove lowering code for unsupported features
e.g. function calls, load/store from stack
Diffstat (limited to 'src/gallium/drivers/radeon/AMDGPUInstrInfo.cpp')
-rw-r--r-- | src/gallium/drivers/radeon/AMDGPUInstrInfo.cpp | 59 |
1 files changed, 3 insertions, 56 deletions
diff --git a/src/gallium/drivers/radeon/AMDGPUInstrInfo.cpp b/src/gallium/drivers/radeon/AMDGPUInstrInfo.cpp index 81b62ccd24d..16dd3525e92 100644 --- a/src/gallium/drivers/radeon/AMDGPUInstrInfo.cpp +++ b/src/gallium/drivers/radeon/AMDGPUInstrInfo.cpp @@ -242,35 +242,7 @@ AMDGPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const { - unsigned int Opc = 0; - // MachineInstr *curMI = MI; - MachineFunction &MF = *(MBB.getParent()); - MachineFrameInfo &MFI = *MF.getFrameInfo(); - - DebugLoc DL; - switch (RC->getID()) { - case AMDGPU::GPRF32RegClassID: - Opc = AMDGPU::PRIVATESTORE_f32; - break; - case AMDGPU::GPRI32RegClassID: - Opc = AMDGPU::PRIVATESTORE_i32; - break; - } - if (MI != MBB.end()) DL = MI->getDebugLoc(); - MachineMemOperand *MMO = - new MachineMemOperand( - MachinePointerInfo::getFixedStack(FrameIndex), - MachineMemOperand::MOLoad, - MFI.getObjectSize(FrameIndex), - MFI.getObjectAlignment(FrameIndex)); - if (MI != MBB.end()) { - DL = MI->getDebugLoc(); - } - BuildMI(MBB, MI, DL, get(Opc)) - .addReg(SrcReg, getKillRegState(isKill)) - .addFrameIndex(FrameIndex) - .addMemOperand(MMO) - .addImm(0); + assert(!"Not Implemented"); } void @@ -279,34 +251,9 @@ AMDGPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const { - unsigned int Opc = 0; - MachineFunction &MF = *(MBB.getParent()); - MachineFrameInfo &MFI = *MF.getFrameInfo(); - DebugLoc DL; - switch (RC->getID()) { - case AMDGPU::GPRF32RegClassID: - Opc = AMDGPU::PRIVATELOAD_f32; - break; - case AMDGPU::GPRI32RegClassID: - Opc = AMDGPU::PRIVATELOAD_i32; - break; - } - - MachineMemOperand *MMO = - new MachineMemOperand( - MachinePointerInfo::getFixedStack(FrameIndex), - MachineMemOperand::MOLoad, - MFI.getObjectSize(FrameIndex), - MFI.getObjectAlignment(FrameIndex)); - if (MI != MBB.end()) { - DL = MI->getDebugLoc(); - } - BuildMI(MBB, MI, DL, get(Opc)) - .addReg(DestReg, RegState::Define) - .addFrameIndex(FrameIndex) - .addMemOperand(MMO) - .addImm(0); + assert(!"Not Implemented"); } + MachineInstr * AMDGPUInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, |