diff options
| author | Tom Stellard <[email protected]> | 2012-07-25 08:30:32 -0400 |
|---|---|---|
| committer | Tom Stellard <[email protected]> | 2012-07-27 17:08:08 +0000 |
| commit | 50ff2dc0a4f553eb8d634d6f081fe5e4e25f6f48 (patch) | |
| tree | acc1b4b0a305aff1f771399445614bf10302fd24 /src/gallium/drivers/radeon/AMDGPUISelLowering.h | |
| parent | c424975572af2edd46863e5bb9fe3c51c96b4f9b (diff) | |
radeon/llvm: Add special nodes for SALU operations on VCC
The VCC register is tricky because the SALU views it as 64-bit, but the
VALU views it as 1-bit. In order to deal with this we've added some
special bitcast and binary operations to help convert from the 64-bit
SALU view to the 1-bit VALU view and vice versa.
Diffstat (limited to 'src/gallium/drivers/radeon/AMDGPUISelLowering.h')
| -rw-r--r-- | src/gallium/drivers/radeon/AMDGPUISelLowering.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeon/AMDGPUISelLowering.h b/src/gallium/drivers/radeon/AMDGPUISelLowering.h index 3e6f9ccaced..63710920418 100644 --- a/src/gallium/drivers/radeon/AMDGPUISelLowering.h +++ b/src/gallium/drivers/radeon/AMDGPUISelLowering.h @@ -71,6 +71,16 @@ enum } // End namespace AMDGPUISD +namespace SIISD { + +enum { + SI_FIRST = AMDGPUISD::LAST_AMDGPU_ISD_NUMBER, + VCC_AND, + VCC_BITCAST +}; + +} // End namespace SIISD + } // End namespace llvm #endif // AMDGPUISELLOWERING_H |