diff options
| author | Tom Stellard <[email protected]> | 2012-07-26 14:30:23 +0000 |
|---|---|---|
| committer | Tom Stellard <[email protected]> | 2012-08-15 18:35:25 +0000 |
| commit | 3aaa209293a281e103ef71e3578fad042972e092 (patch) | |
| tree | 1a7e3557ac03276cccb10ca0ab0521714ba5f530 /src/gallium/drivers/radeon/AMDGPUISelLowering.cpp | |
| parent | 40c41fe890e53d99afb4e2c3fbf10043081edd9e (diff) | |
radeon/llvm: Lower loads from USE_SGPR adddress space during DAG lowering
Diffstat (limited to 'src/gallium/drivers/radeon/AMDGPUISelLowering.cpp')
| -rw-r--r-- | src/gallium/drivers/radeon/AMDGPUISelLowering.cpp | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp index 2e6782840f2..e22df8efb0e 100644 --- a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp +++ b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp @@ -311,13 +311,6 @@ bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const return false; } -void AMDGPUTargetLowering::addLiveIn(MachineInstr * MI, - MachineFunction * MF, MachineRegisterInfo & MRI, - const TargetInstrInfo * TII, unsigned reg) const -{ - AMDGPU::utilAddLiveIn(MF, MRI, TII, reg, MI->getOperand(0).getReg()); -} - SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const { |