diff options
| author | Tom Stellard <[email protected]> | 2012-09-11 15:24:32 -0400 |
|---|---|---|
| committer | Tom Stellard <[email protected]> | 2012-09-13 10:38:02 -0400 |
| commit | 6a5a4d59ce63aa1fa14d3dd6c50169c532424b6d (patch) | |
| tree | ba0e1c5952a7969ae30fdf3be6c7d90bf2c73778 /src/gallium/drivers/radeon/AMDGPUISelLowering.cpp | |
| parent | 70a50685a8f7934e23978ac34dcefcfab46c69de (diff) | |
radeon/llvm: Fix lowering of vbuild
Some of the old AMDIL code was hard-coding subreg indices when creating
the VBUILD node, which was making it difficult to match the
vector_insert patterns.
Diffstat (limited to 'src/gallium/drivers/radeon/AMDGPUISelLowering.cpp')
| -rw-r--r-- | src/gallium/drivers/radeon/AMDGPUISelLowering.cpp | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp index 0a70164fcbf..59daf77503e 100644 --- a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp +++ b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp @@ -88,7 +88,6 @@ SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) // AMDIL DAG lowering case ISD::SDIV: return LowerSDIV(Op, DAG); case ISD::SREM: return LowerSREM(Op, DAG); - case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG); case ISD::BRCOND: return LowerBRCOND(Op, DAG); // AMDGPU DAG lowering @@ -336,7 +335,6 @@ const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const NODE_NAME_CASE(CALL); NODE_NAME_CASE(UMUL); NODE_NAME_CASE(DIV_INF); - NODE_NAME_CASE(VBUILD); NODE_NAME_CASE(RET_FLAG); NODE_NAME_CASE(BRANCH_COND); |