diff options
| author | Marek Olšák <[email protected]> | 2017-06-06 23:54:23 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2017-06-08 23:29:07 +0200 |
| commit | 69403617963681ed48fa937e978919b855aa4049 (patch) | |
| tree | 53adc06ea5548244e06dd29432b1a23f1e16e6a5 /src/gallium/drivers/r600 | |
| parent | c6451b12096fb4258051b9b38c50ffb0a86df173 (diff) | |
gallium/radeon: don't allocate HTILE in a separate buffer
Reviewed-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src/gallium/drivers/r600')
| -rw-r--r-- | src/gallium/drivers/r600/evergreen_state.c | 6 | ||||
| -rw-r--r-- | src/gallium/drivers/r600/r600_blit.c | 2 | ||||
| -rw-r--r-- | src/gallium/drivers/r600/r600_state.c | 6 |
3 files changed, 7 insertions, 7 deletions
diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index c3b939fc72e..95953515ac2 100644 --- a/src/gallium/drivers/r600/evergreen_state.c +++ b/src/gallium/drivers/r600/evergreen_state.c @@ -1393,8 +1393,8 @@ static void evergreen_init_depth_surface(struct r600_context *rctx, } /* use htile only for first level */ - if (rtex->htile_buffer && !level) { - uint64_t va = rtex->htile_buffer->gpu_address; + if (rtex->htile_offset && !level) { + uint64_t va = rtex->resource.gpu_address + rtex->htile_offset; surf->db_htile_data_base = va >> 8; surf->db_htile_surface = S_028ABC_HTILE_WIDTH(1) | S_028ABC_HTILE_HEIGHT(1) | @@ -1876,7 +1876,7 @@ static void evergreen_emit_db_state(struct r600_context *rctx, struct r600_atom radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, a->rsurf->db_htile_surface); radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, a->rsurf->db_preload_control); radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base); - reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rtex->htile_buffer, + reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, &rtex->resource, RADEON_USAGE_READWRITE, RADEON_PRIO_HTILE); radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); radeon_emit(cs, reloc_idx); diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c index 80aa9c05769..79505d501d0 100644 --- a/src/gallium/drivers/r600/r600_blit.c +++ b/src/gallium/drivers/r600/r600_blit.c @@ -444,7 +444,7 @@ static void r600_clear(struct pipe_context *ctx, unsigned buffers, * disable fast clear for texture array. */ /* Only use htile for first level */ - if (rtex->htile_buffer && !level && + if (rtex->htile_offset && !level && fb->zsbuf->u.tex.first_layer == 0 && fb->zsbuf->u.tex.last_layer == util_max_layer(&rtex->resource.b.b, level)) { if (rtex->depth_clear_value != depth) { diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c index 2001cfd512a..dca8fe5e5bc 100644 --- a/src/gallium/drivers/r600/r600_state.c +++ b/src/gallium/drivers/r600/r600_state.c @@ -1061,8 +1061,8 @@ static void r600_init_depth_surface(struct r600_context *rctx, surf->db_prefetch_limit = (rtex->surface.u.legacy.level[level].nblk_y / 8) - 1; /* use htile only for first level */ - if (rtex->htile_buffer && !level) { - surf->db_htile_data_base = 0; + if (rtex->htile_offset && !level) { + surf->db_htile_data_base = rtex->htile_offset >> 8; surf->db_htile_surface = S_028D24_HTILE_WIDTH(1) | S_028D24_HTILE_HEIGHT(1) | S_028D24_FULL_CACHE(1); @@ -1543,7 +1543,7 @@ static void r600_emit_db_state(struct r600_context *rctx, struct r600_atom *atom radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value)); radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, a->rsurf->db_htile_surface); radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base); - reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rtex->htile_buffer, + reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, &rtex->resource, RADEON_USAGE_READWRITE, RADEON_PRIO_HTILE); radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); radeon_emit(cs, reloc_idx); |