diff options
| author | Marek Olšák <[email protected]> | 2017-08-19 15:28:14 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2017-08-22 13:29:47 +0200 |
| commit | e96259fabec0d9f8d20d21bca5b01f1ea41d3965 (patch) | |
| tree | a80c95cfd3d2d69b04e17a922048e3bae9349128 /src/gallium/drivers/r600 | |
| parent | 7dec48b81e88dc933a23d12d3a71a4c6b9f216e4 (diff) | |
gallium/radeon: add helpers for whether HTILE is enabled
Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src/gallium/drivers/r600')
| -rw-r--r-- | src/gallium/drivers/r600/evergreen_state.c | 3 | ||||
| -rw-r--r-- | src/gallium/drivers/r600/r600_blit.c | 3 | ||||
| -rw-r--r-- | src/gallium/drivers/r600/r600_state.c | 3 |
3 files changed, 3 insertions, 6 deletions
diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index 764acfcad75..a9b503f9f10 100644 --- a/src/gallium/drivers/r600/evergreen_state.c +++ b/src/gallium/drivers/r600/evergreen_state.c @@ -1392,8 +1392,7 @@ static void evergreen_init_depth_surface(struct r600_context *rctx, S_028044_FORMAT(V_028044_STENCIL_8); } - /* use htile only for first level */ - if (rtex->htile_offset && !level) { + if (r600_htile_enabled(rtex, level)) { uint64_t va = rtex->resource.gpu_address + rtex->htile_offset; surf->db_htile_data_base = va >> 8; surf->db_htile_surface = S_028ABC_HTILE_WIDTH(1) | diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c index 79505d501d0..783d8c8a3bc 100644 --- a/src/gallium/drivers/r600/r600_blit.c +++ b/src/gallium/drivers/r600/r600_blit.c @@ -443,8 +443,7 @@ static void r600_clear(struct pipe_context *ctx, unsigned buffers, * array are clear to different value. To simplify code just * disable fast clear for texture array. */ - /* Only use htile for first level */ - if (rtex->htile_offset && !level && + if (r600_htile_enabled(rtex, level) && fb->zsbuf->u.tex.first_layer == 0 && fb->zsbuf->u.tex.last_layer == util_max_layer(&rtex->resource.b.b, level)) { if (rtex->depth_clear_value != depth) { diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c index 300dbe8040c..c21e8dabb1f 100644 --- a/src/gallium/drivers/r600/r600_state.c +++ b/src/gallium/drivers/r600/r600_state.c @@ -1060,8 +1060,7 @@ static void r600_init_depth_surface(struct r600_context *rctx, surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice); surf->db_prefetch_limit = (rtex->surface.u.legacy.level[level].nblk_y / 8) - 1; - /* use htile only for first level */ - if (rtex->htile_offset && !level) { + if (r600_htile_enabled(rtex, level)) { surf->db_htile_data_base = rtex->htile_offset >> 8; surf->db_htile_surface = S_028D24_HTILE_WIDTH(1) | S_028D24_HTILE_HEIGHT(1) | |