Merge remote-tracking branch 'origin/master' into pipe-video

Conflicts:
	src/gallium/tests/unit/u_format_test.c
	src/gallium/winsys/r600/drm/r600_hw_context.c

7 files changed, 190 insertions, 203 deletions

diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 54f5410c324..9ebfe54c76d 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -380,9 +380,8 @@ static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_conte
 							struct pipe_resource *texture,
 							const struct pipe_sampler_view *state)
 {
-	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 	struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
-	struct r600_pipe_state *rstate;
+	struct r600_pipe_resource_state *rstate;
 	const struct util_format_description *desc;
 	struct r600_resource_texture *tmp;
 	struct r600_resource *rbuffer;
@@ -438,35 +437,27 @@ static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_conte
 	array_mode = tmp->array_mode[0];
 	tile_type = tmp->tile_type;
 
-	r600_pipe_state_add_reg(rstate, R_030000_RESOURCE0_WORD0,
-				S_030000_DIM(r600_tex_dim(texture->target)) |
-				S_030000_PITCH((pitch / 8) - 1) |
-				S_030000_NON_DISP_TILING_ORDER(tile_type) |
-				S_030000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R_030004_RESOURCE0_WORD1,
-				S_030004_TEX_HEIGHT(texture->height0 - 1) |
-				S_030004_TEX_DEPTH(texture->depth0 - 1) |
-				S_030004_ARRAY_MODE(array_mode),
-				0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R_030008_RESOURCE0_WORD2,
-				(tmp->offset[0] + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
-	r600_pipe_state_add_reg(rstate, R_03000C_RESOURCE0_WORD3,
-				(tmp->offset[1] + r600_bo_offset(bo[1])) >> 8, 0xFFFFFFFF, bo[1]);
-	r600_pipe_state_add_reg(rstate, R_030010_RESOURCE0_WORD4,
-				word4 |
-				S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
-				S_030010_ENDIAN_SWAP(endian) |
-				S_030010_BASE_LEVEL(state->u.tex.first_level), 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R_030014_RESOURCE0_WORD5,
-				S_030014_LAST_LEVEL(state->u.tex.last_level) |
-				S_030014_BASE_ARRAY(0) |
-				S_030014_LAST_ARRAY(0), 0xffffffff, NULL);
-	r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6,
-				S_030018_MAX_ANISO(4 /* max 16 samples */),
-				0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R_03001C_RESOURCE0_WORD7,
-				S_03001C_DATA_FORMAT(format) |
-				S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL);
+	rstate->bo[0] = bo[0];
+	rstate->bo[1] = bo[1];
+	rstate->val[0] = (S_030000_DIM(r600_tex_dim(texture->target)) |
+			  S_030000_PITCH((pitch / 8) - 1) |
+			  S_030000_NON_DISP_TILING_ORDER(tile_type) |
+			  S_030000_TEX_WIDTH(texture->width0 - 1));
+	rstate->val[1] = (S_030004_TEX_HEIGHT(texture->height0 - 1) |
+			  S_030004_TEX_DEPTH(texture->depth0 - 1) |
+			  S_030004_ARRAY_MODE(array_mode));
+	rstate->val[2] = (tmp->offset[0] + r600_bo_offset(bo[0])) >> 8;
+	rstate->val[3] = (tmp->offset[1] + r600_bo_offset(bo[1])) >> 8;
+	rstate->val[4] = (word4 |
+			  S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
+			  S_030010_ENDIAN_SWAP(endian) |
+			  S_030010_BASE_LEVEL(state->u.tex.first_level));
+	rstate->val[5] = (S_030014_LAST_LEVEL(state->u.tex.last_level) |
+			  S_030014_BASE_ARRAY(0) |
+			  S_030014_LAST_ARRAY(0));
+	rstate->val[6] = (S_030018_MAX_ANISO(4 /* max 16 samples */));
+	rstate->val[7] = (S_03001C_DATA_FORMAT(format) |
+			  S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE));
 
 	return &resource->base;
 }
@@ -1032,7 +1023,10 @@ static void cayman_init_config(struct r600_pipe_context *rctx)
 	tmp |= S_008C00_EXPORT_SRC_C(1);
 	r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
 
-	r600_pipe_state_add_reg(rstate, CM_R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, (4 << 28), 0xFFFFFFFF, NULL);
+	/* always set the temp clauses */
+	r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, S_008C04_NUM_CLAUSE_TEMP_GPRS(4), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, 0, 0xFFFFFFFF, NULL);
 	r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8), 0xFFFFFFFF, NULL);
 
 	r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0, 0x0, 0xFFFFFFFF, NULL);
@@ -1384,21 +1378,38 @@ void evergreen_init_config(struct r600_pipe_context *rctx)
 	tmp |= S_008C00_ES_PRIO(es_prio);
 	r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
 
-	tmp = 0;
-	tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
-	tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
-	tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
-	r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
-
-	tmp = 0;
-	tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
-	tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
-	r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
-
-	tmp = 0;
-	tmp |= S_008C0C_NUM_HS_GPRS(num_hs_gprs);
-	tmp |= S_008C0C_NUM_LS_GPRS(num_ls_gprs);
-	r600_pipe_state_add_reg(rstate, R_008C0C_SQ_GPR_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
+	/* enable dynamic GPR resource management */
+	if (r600_get_minor_version(rctx->radeon) >= 7) {
+		/* always set temp clauses */
+		r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1,
+					S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs), 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 0, 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, 0, 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8), 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
+					S_028838_PS_GPRS(0x1e) |
+					S_028838_VS_GPRS(0x1e) |
+					S_028838_GS_GPRS(0x1e) |
+					S_028838_ES_GPRS(0x1e) |
+					S_028838_HS_GPRS(0x1e) |
+					S_028838_LS_GPRS(0x1e), 0xFFFFFFFF, NULL); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
+	} else {
+		tmp = 0;
+		tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
+		tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
+		tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
+		r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
+
+		tmp = 0;
+		tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
+		tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
+		r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
+
+		tmp = 0;
+		tmp |= S_008C0C_NUM_HS_GPRS(num_hs_gprs);
+		tmp |= S_008C0C_NUM_HS_GPRS(num_ls_gprs);
+		r600_pipe_state_add_reg(rstate, R_008C0C_SQ_GPR_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
+	}
 
 	tmp = 0;
 	tmp |= S_008C18_NUM_PS_THREADS(num_ps_threads);
@@ -1769,45 +1780,32 @@ void *evergreen_create_db_flush_dsa(struct r600_pipe_context *rctx)
 }
 
 void evergreen_pipe_init_buffer_resource(struct r600_pipe_context *rctx,
-					 struct r600_pipe_state *rstate,
-					 struct r600_resource *rbuffer,
-					 unsigned offset, unsigned stride)
+					 struct r600_pipe_resource_state *rstate)
 {
 	rstate->id = R600_PIPE_STATE_RESOURCE;
-	rstate->nregs = 0;
-	r600_pipe_state_add_reg(rstate, R_030000_RESOURCE0_WORD0,
-				offset, 0xFFFFFFFF, rbuffer->bo);
-	r600_pipe_state_add_reg(rstate, R_030004_RESOURCE0_WORD1,
-				rbuffer->bo_size - offset - 1, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R_030008_RESOURCE0_WORD2,
-				S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
-				S_030008_STRIDE(stride), 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R_03000C_RESOURCE0_WORD3,
-				S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
-				S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
-				S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
-				S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W),
-				0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R_030010_RESOURCE0_WORD4,
-				0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R_030014_RESOURCE0_WORD5,
-				0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6,
-				0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R_03001C_RESOURCE0_WORD7,
-				0xC0000000, 0xFFFFFFFF, NULL);
+
+	rstate->val[0] = 0;
+	rstate->bo[0] = NULL;
+	rstate->val[1] = 0;
+	rstate->val[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32));
+	rstate->val[3] = S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
+	  S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
+	  S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
+	  S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W);
+	rstate->val[4] = 0;
+	rstate->val[5] = 0;
+	rstate->val[6] = 0;
+	rstate->val[7] = 0xc0000000;
 }
 
 
-void evergreen_pipe_mod_buffer_resource(struct r600_pipe_state *rstate,
+void evergreen_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate,
 					struct r600_resource *rbuffer,
 					unsigned offset, unsigned stride)
 {
-	rstate->nregs = 0;
-	r600_pipe_state_mod_reg_bo(rstate, offset, rbuffer->bo);
-	r600_pipe_state_mod_reg(rstate, rbuffer->bo_size - offset - 1);
-	r600_pipe_state_mod_reg(rstate, S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
-				S_030008_STRIDE(stride));
-	rstate->nregs = 8;
-
+	rstate->bo[0] = rbuffer->bo;
+	rstate->val[0] = offset;
+	rstate->val[1] = rbuffer->bo_size - offset - 1;
+	rstate->val[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
+	                 S_030008_STRIDE(stride);
 }
diff --git a/src/gallium/drivers/r600/evergreend.h b/src/gallium/drivers/r600/evergreend.h
index ee0c7c9ed9b..d795f5757ed 100644
--- a/src/gallium/drivers/r600/evergreend.h
+++ b/src/gallium/drivers/r600/evergreend.h
@@ -171,6 +171,10 @@
 #define   S_008C0C_NUM_LS_GPRS(x)                      (((x) & 0xFF) << 16)
 #define   G_008C0C_NUM_LS_GPRS(x)                      (((x) >> 16) & 0xFF)
 #define   C_008C0C_NUM_LS_GPRS(x)                      0xFF00FFFF
+
+#define R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1       0x00008C10
+#define R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2       0x00008C14
+
 #define R_008C18_SQ_THREAD_RESOURCE_MGMT_1           0x00008C18
 #define   S_008C18_NUM_PS_THREADS(x)                   (((x) & 0xFF) << 0)
 #define   G_008C18_NUM_PS_THREADS(x)                   (((x) >> 0) & 0xFF)
@@ -1637,6 +1641,12 @@
 #define R_028818_PA_CL_VTE_CNTL                      0x00028818
 #define R_028820_PA_CL_NANINF_CNTL                   0x00028820
 #define R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1         0x00028838
+#define   S_028838_PS_GPRS(x)                          (((x) & 0x1F) << 0)
+#define   S_028838_VS_GPRS(x)                          (((x) & 0x1F) << 5)
+#define   S_028838_GS_GPRS(x)                          (((x) & 0x1F) << 10)
+#define   S_028838_ES_GPRS(x)                          (((x) & 0x1F) << 15)
+#define   S_028838_HS_GPRS(x)                          (((x) & 0x1F) << 20)
+#define   S_028838_LS_GPRS(x)                          (((x) & 0x1F) << 25)
 #define R_028840_SQ_PGM_START_PS                     0x00028840
 #define R_02884C_SQ_PGM_EXPORTS_PS                   0x0002884C
 #define   S_02884C_EXPORT_COLORS(x)                    (((x) & 0xF) << 1)
@@ -1948,6 +1958,4 @@
 #define CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0 0x28c38
 #define CM_R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1 0x28c3c
 
-#define CM_R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1              0x00008C10
-#define CM_R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2              0x00008C14
 #endif
diff --git a/src/gallium/drivers/r600/r600.h b/src/gallium/drivers/r600/r600.h
index 23e7181a86e..bf7138d9e4e 100644
--- a/src/gallium/drivers/r600/r600.h
+++ b/src/gallium/drivers/r600/r600.h
@@ -30,6 +30,7 @@
 #include <stdint.h>
 #include <stdio.h>
 #include <util/u_double_list.h>
+#include <util/u_inlines.h>
 #include <pipe/p_compiler.h>
 
 #define RADEON_CTX_MAX_PM4	(64 * 1024 / 4)
@@ -47,33 +48,6 @@ struct winsys_handle;
 
 enum radeon_family {
 	CHIP_UNKNOWN,
-	CHIP_R100,
-	CHIP_RV100,
-	CHIP_RS100,
-	CHIP_RV200,
-	CHIP_RS200,
-	CHIP_R200,
-	CHIP_RV250,
-	CHIP_RS300,
-	CHIP_RV280,
-	CHIP_R300,
-	CHIP_R350,
-	CHIP_RV350,
-	CHIP_RV380,
-	CHIP_R420,
-	CHIP_R423,
-	CHIP_RV410,
-	CHIP_RS400,
-	CHIP_RS480,
-	CHIP_RS600,
-	CHIP_RS690,
-	CHIP_RS740,
-	CHIP_RV515,
-	CHIP_R520,
-	CHIP_RV530,
-	CHIP_RV560,
-	CHIP_RV570,
-	CHIP_R580,
 	CHIP_R600,
 	CHIP_RV610,
 	CHIP_RV630,
@@ -130,14 +104,24 @@ struct r600_bo *r600_bo_handle(struct radeon *radeon,
 				unsigned handle, unsigned *array_mode);
 void *r600_bo_map(struct radeon *radeon, struct r600_bo *bo, unsigned usage, void *ctx);
 void r600_bo_unmap(struct radeon *radeon, struct r600_bo *bo);
-void r600_bo_reference(struct radeon *radeon, struct r600_bo **dst,
-			    struct r600_bo *src);
 boolean r600_bo_get_winsys_handle(struct radeon *radeon, struct r600_bo *pb_bo,
 				unsigned stride, struct winsys_handle *whandle);
 static INLINE unsigned r600_bo_offset(struct r600_bo *bo)
 {
 	return 0;
 }
+void r600_bo_destroy(struct radeon *radeon, struct r600_bo *bo);
+
+/* this relies on the pipe_reference being the first member of r600_bo */
+static INLINE void r600_bo_reference(struct radeon *radeon, struct r600_bo **dst, struct r600_bo *src)
+{
+	struct r600_bo *old = *dst;
+
+	if (pipe_reference((struct pipe_reference *)(*dst), (struct pipe_reference *)src)) {
+		r600_bo_destroy(radeon, old);
+	}
+	*dst = src;
+}
 
 
 /* R600/R700 STATES */
@@ -170,8 +154,17 @@ struct r600_pipe_state {
 	struct r600_pipe_reg		regs[R600_BLOCK_MAX_REG];
 };
 
+struct r600_pipe_resource_state {
+	unsigned			id;
+	u32                             val[8];
+	struct r600_bo *bo[2];
+};
+
 #define R600_BLOCK_STATUS_ENABLED	(1 << 0)
 #define R600_BLOCK_STATUS_DIRTY		(1 << 1)
+#define R600_BLOCK_STATUS_RESOURCE_DIRTY	(1 << 2)
+
+#define R600_BLOCK_STATUS_RESOURCE_VERTEX	(1 << 3)
 
 struct r600_block_reloc {
 	struct r600_bo		*bo;
@@ -182,6 +175,7 @@ struct r600_block_reloc {
 
 struct r600_block {
 	struct list_head	list;
+	struct list_head	enable_list;
 	unsigned		status;
 	unsigned                flags;
 	unsigned		start_offset;
@@ -245,6 +239,8 @@ struct r600_context {
 	unsigned		nblocks;
 	struct r600_block	**blocks;
 	struct list_head	dirty;
+	struct list_head	resource_dirty;
+	struct list_head	enable_list;
 	unsigned		pm4_ndwords;
 	unsigned		pm4_cdwords;
 	unsigned		pm4_dirty_cdwords;
@@ -261,6 +257,10 @@ struct r600_context {
 	unsigned                num_dest_buffers;
 	unsigned		flags;
 	boolean                 predicate_drawing;
+	struct r600_range ps_resources;
+	struct r600_range vs_resources;
+	struct r600_range fs_resources;
+	int num_ps_resources, num_vs_resources, num_fs_resources;
 };
 
 struct r600_draw {
@@ -275,9 +275,9 @@ struct r600_draw {
 int r600_context_init(struct r600_context *ctx, struct radeon *radeon);
 void r600_context_fini(struct r600_context *ctx);
 void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state);
-void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
-void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
-void r600_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
+void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
+void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
+void r600_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
 void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 void r600_context_flush(struct r600_context *ctx);
@@ -303,9 +303,9 @@ void r600_context_flush_dest_caches(struct r600_context *ctx);
 int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon);
 void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *draw);
 void evergreen_context_flush_dest_caches(struct r600_context *ctx);
-void evergreen_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
-void evergreen_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
-void evergreen_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
+void evergreen_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
+void evergreen_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
+void evergreen_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
 void evergreen_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 void evergreen_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 
diff --git a/src/gallium/drivers/r600/r600_asm.c b/src/gallium/drivers/r600/r600_asm.c
index 65e539eba35..3196d97dbbb 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -1088,7 +1088,7 @@ static int r600_bc_alloc_kcache_lines(struct r600_bc *bc, struct r600_bc_alu *al
 
 	/* Collect required cache lines. */
 	for (i = 0; i < 3; ++i) {
-		bool found = false;
+		boolean found = false;
 		unsigned int line;
 
 		if (alu->src[i].sel < 512)
@@ -1140,7 +1140,7 @@ static int r600_bc_alloc_kcache_lines(struct r600_bc *bc, struct r600_bc_alu *al
 
 	/* Setup the kcache lines. */
 	for (i = 0; i < count; ++i) {
-		bool found = false;
+		boolean found = false;
 
 		for (j = 0; j < 2; ++j) {
 			if (kcache[j].mode == V_SQ_CF_KCACHE_LOCK_2 &&
diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h
index 8002d943abd..d92b74ebc4e 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -82,12 +82,12 @@ struct r600_screen {
 
 struct r600_pipe_sampler_view {
 	struct pipe_sampler_view	base;
-	struct r600_pipe_state		state;
+	struct r600_pipe_resource_state		state;
 };
 
 struct r600_pipe_rasterizer {
 	struct r600_pipe_state		rstate;
-	bool				flatshade;
+	boolean				flatshade;
 	unsigned			sprite_coord_enable;
 	float				offset_units;
 	float				offset_scale;
@@ -173,7 +173,7 @@ struct r600_pipe_context {
 	struct r600_pipe_state		*states[R600_PIPE_NSTATES];
 	struct r600_context		ctx;
 	struct r600_vertex_element	*vertex_elements;
-	struct r600_pipe_state		fs_resource[PIPE_MAX_ATTRIBS];
+	struct r600_pipe_resource_state		fs_resource[PIPE_MAX_ATTRIBS];
 	struct pipe_framebuffer_state	framebuffer;
 	struct pipe_index_buffer	index_buffer;
 	unsigned			cb_target_mask;
@@ -185,25 +185,25 @@ struct r600_pipe_context {
 	struct r600_pipe_shader 	*ps_shader;
 	struct r600_pipe_shader 	*vs_shader;
 	struct r600_pipe_state		vs_const_buffer;
-	struct r600_pipe_state		vs_const_buffer_resource[R600_MAX_CONST_BUFFERS];
+	struct r600_pipe_resource_state		vs_const_buffer_resource[R600_MAX_CONST_BUFFERS];
 	struct r600_pipe_state		ps_const_buffer;
-	struct r600_pipe_state		ps_const_buffer_resource[R600_MAX_CONST_BUFFERS];
+	struct r600_pipe_resource_state		ps_const_buffer_resource[R600_MAX_CONST_BUFFERS];
 	struct r600_pipe_rasterizer	*rasterizer;
 	struct r600_pipe_state          vgt;
 	struct r600_pipe_state          spi;
 	/* shader information */
 	unsigned			sprite_coord_enable;
-	bool				flatshade;
-	bool				export_16bpc;
+	boolean				flatshade;
+	boolean				export_16bpc;
 	unsigned			alpha_ref;
-	bool				alpha_ref_dirty;
+	boolean				alpha_ref_dirty;
 	struct r600_textures_info	ps_samplers;
 
 	struct r600_pipe_fences		fences;
 
 	struct u_vbuf_mgr		*vbuf_mgr;
 	struct util_slab_mempool	pool_transfers;
-	bool				blit;
+	boolean				blit;
 
 };
 
@@ -224,10 +224,8 @@ void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element
 void *evergreen_create_db_flush_dsa(struct r600_pipe_context *rctx);
 void evergreen_polygon_offset_update(struct r600_pipe_context *rctx);
 void evergreen_pipe_init_buffer_resource(struct r600_pipe_context *rctx,
-				    struct r600_pipe_state *rstate,
-				    struct r600_resource *rbuffer,
-				    unsigned offset, unsigned stride);
-void evergreen_pipe_mod_buffer_resource(struct r600_pipe_state *rstate,
+					 struct r600_pipe_resource_state *rstate);
+void evergreen_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate,
 					struct r600_resource *rbuffer,
 					unsigned offset, unsigned stride);
 
@@ -268,10 +266,8 @@ void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve)
 void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx);
 void r600_polygon_offset_update(struct r600_pipe_context *rctx);
 void r600_pipe_init_buffer_resource(struct r600_pipe_context *rctx,
-				    struct r600_pipe_state *rstate,
-				    struct r600_resource *rbuffer,
-				    unsigned offset, unsigned stride);
-void r600_pipe_mod_buffer_resource(struct r600_pipe_state *rstate,
+				    struct r600_pipe_resource_state *rstate);
+void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate,
 				   struct r600_resource *rbuffer,
 				   unsigned offset, unsigned stride);
 
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 46fdbfed34a..a6cfa704ca5 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -414,7 +414,7 @@ static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *c
 {
 	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 	struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
-	struct r600_pipe_state *rstate;
+	struct r600_pipe_resource_state *rstate;
 	const struct util_format_description *desc;
 	struct r600_resource_texture *tmp;
 	struct r600_resource *rbuffer;
@@ -477,33 +477,29 @@ static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *c
 		depth = texture->array_size;
 	}
 
-	r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0,
-				S_038000_DIM(r600_tex_dim(texture->target)) |
-				S_038000_TILE_MODE(array_mode) |
-				S_038000_TILE_TYPE(tile_type) |
-				S_038000_PITCH((pitch / 8) - 1) |
-				S_038000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R_038004_RESOURCE0_WORD1,
-				S_038004_TEX_HEIGHT(height - 1) |
-				S_038004_TEX_DEPTH(depth - 1) |
-				S_038004_DATA_FORMAT(format), 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R_038008_RESOURCE0_WORD2,
-				(tmp->offset[0] + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
-	r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3,
-				(tmp->offset[1] + r600_bo_offset(bo[1])) >> 8, 0xFFFFFFFF, bo[1]);
-	r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4,
-				word4 |
-				S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
-				S_038010_REQUEST_SIZE(1) |
-				S_038010_ENDIAN_SWAP(endian) |
-				S_038010_BASE_LEVEL(state->u.tex.first_level), 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R_038014_RESOURCE0_WORD5,
-				S_038014_LAST_LEVEL(state->u.tex.last_level) |
-				S_038014_BASE_ARRAY(state->u.tex.first_layer) |
-				S_038014_LAST_ARRAY(state->u.tex.last_layer), 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6,
-				S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
-				S_038018_MAX_ANISO(4 /* max 16 samples */), 0xFFFFFFFF, NULL);
+	rstate->bo[0] = bo[0];
+	rstate->bo[1] = bo[1];
+
+	rstate->val[0] = (S_038000_DIM(r600_tex_dim(texture->target)) |
+			  S_038000_TILE_MODE(array_mode) |
+			  S_038000_TILE_TYPE(tile_type) |
+			  S_038000_PITCH((pitch / 8) - 1) |
+			  S_038000_TEX_WIDTH(texture->width0 - 1));
+	rstate->val[1] = (S_038004_TEX_HEIGHT(height - 1) |
+			  S_038004_TEX_DEPTH(depth - 1) |
+			  S_038004_DATA_FORMAT(format));
+	rstate->val[2] = (tmp->offset[0] + r600_bo_offset(bo[0])) >> 8;
+	rstate->val[3] = (tmp->offset[1] + r600_bo_offset(bo[1])) >> 8;
+	rstate->val[4] = (word4 |
+			  S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
+			  S_038010_REQUEST_SIZE(1) |
+			  S_038010_ENDIAN_SWAP(endian) |
+			  S_038010_BASE_LEVEL(state->u.tex.first_level));
+	rstate->val[5] = (S_038014_LAST_LEVEL(state->u.tex.last_level) |
+			  S_038014_BASE_ARRAY(state->u.tex.first_layer) |
+			  S_038014_LAST_ARRAY(state->u.tex.last_layer));
+	rstate->val[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
+			  S_038018_MAX_ANISO(4 /* max 16 samples */));
 
 	return &resource->base;
 }
@@ -1486,37 +1482,27 @@ void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx)
 }
 
 void r600_pipe_init_buffer_resource(struct r600_pipe_context *rctx,
-				    struct r600_pipe_state *rstate,
-				    struct r600_resource *rbuffer,
-				    unsigned offset, unsigned stride)
+				    struct r600_pipe_resource_state *rstate)
 {
 	rstate->id = R600_PIPE_STATE_RESOURCE;
-	rstate->nregs = 0;
-	r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0,
-				offset, 0xFFFFFFFF, rbuffer->bo);
-	r600_pipe_state_add_reg(rstate, R_038004_RESOURCE0_WORD1,
-				rbuffer->bo_size - offset - 1, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R_038008_RESOURCE0_WORD2,
-				S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
-				S_038008_STRIDE(stride), 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3,
-				0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4,
-				0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R_038014_RESOURCE0_WORD5,
-				0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6,
-				0xC0000000, 0xFFFFFFFF, NULL);
+
+	rstate->bo[0] = NULL;
+	rstate->val[0] = 0;
+	rstate->val[1] = 0;
+	rstate->val[2] = 0;
+	rstate->val[3] = 0;
+	rstate->val[4] = 0;
+	rstate->val[5] = 0;
+	rstate->val[6] = 0xc0000000;
 }
 
-void r600_pipe_mod_buffer_resource(struct r600_pipe_state *rstate,
+void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate,
 				   struct r600_resource *rbuffer,
 				   unsigned offset, unsigned stride)
 {
-	rstate->nregs = 0;
-	r600_pipe_state_mod_reg_bo(rstate, offset, rbuffer->bo);
-	r600_pipe_state_mod_reg(rstate, rbuffer->bo_size - offset - 1);
-	r600_pipe_state_mod_reg(rstate, S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
-				S_038008_STRIDE(stride));
-	rstate->nregs = 7;
+	rstate->val[0] = offset;
+	rstate->bo[0] = rbuffer->bo;
+	rstate->val[1] = rbuffer->bo_size - offset - 1;
+	rstate->val[2] = S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
+	                 S_038008_STRIDE(stride);
 }
diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c
index 48ab15f9323..a670ac02be2 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -318,12 +318,10 @@ void r600_delete_vs_shader(struct pipe_context *ctx, void *state)
 
 static void r600_update_alpha_ref(struct r600_pipe_context *rctx)
 {
-	unsigned alpha_ref = rctx->alpha_ref;
+	unsigned alpha_ref;
 	struct r600_pipe_state rstate;
 
-	if (!rctx->alpha_ref_dirty)
-		return;
-
+	alpha_ref = rctx->alpha_ref;
 	rstate.nregs = 0;
 	if (rctx->export_16bpc)
 		alpha_ref &= ~0x1FFF;
@@ -388,7 +386,7 @@ void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
 {
 	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 	struct r600_resource_buffer *rbuffer = r600_buffer(buffer);
-	struct r600_pipe_state *rstate;
+	struct r600_pipe_resource_state *rstate;
 	uint32_t offset;
 
 	/* Note that the state tracker can unbind constant buffers by
@@ -416,9 +414,9 @@ void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
 		rstate = &rctx->vs_const_buffer_resource[index];
 		if (!rstate->id) {
 			if (rctx->family >= CHIP_CEDAR) {
-				evergreen_pipe_init_buffer_resource(rctx, rstate, &rbuffer->r, offset, 16);
+				evergreen_pipe_init_buffer_resource(rctx, rstate);
 			} else {
-				r600_pipe_init_buffer_resource(rctx, rstate, &rbuffer->r, offset, 16);
+				r600_pipe_init_buffer_resource(rctx, rstate);
 			}
 		}
 
@@ -444,9 +442,9 @@ void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
 		rstate = &rctx->ps_const_buffer_resource[index];
 		if (!rstate->id) {
 			if (rctx->family >= CHIP_CEDAR) {
-				evergreen_pipe_init_buffer_resource(rctx, rstate, &rbuffer->r, offset, 16);
+				evergreen_pipe_init_buffer_resource(rctx, rstate);
 			} else {
-				r600_pipe_init_buffer_resource(rctx, rstate, &rbuffer->r, offset, 16);
+				r600_pipe_init_buffer_resource(rctx, rstate);
 			}
 		}
 		if (rctx->family >= CHIP_CEDAR) {
@@ -468,7 +466,7 @@ void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
 
 static void r600_vertex_buffer_update(struct r600_pipe_context *rctx)
 {
-	struct r600_pipe_state *rstate;
+	struct r600_pipe_resource_state *rstate;
 	struct r600_resource *rbuffer;
 	struct pipe_vertex_buffer *vertex_buffer;
 	unsigned i, count, offset;
@@ -503,9 +501,9 @@ static void r600_vertex_buffer_update(struct r600_pipe_context *rctx)
 
 		if (!rstate->id) {
 			if (rctx->family >= CHIP_CEDAR) {
-				evergreen_pipe_init_buffer_resource(rctx, rstate, rbuffer, offset, vertex_buffer->stride);
+				evergreen_pipe_init_buffer_resource(rctx, rstate);
 			} else {
-				r600_pipe_init_buffer_resource(rctx, rstate, rbuffer, offset, vertex_buffer->stride);
+				r600_pipe_init_buffer_resource(rctx, rstate);
 			}
 		}
 
@@ -595,7 +593,8 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
 		return;
 	}
 
-	r600_update_alpha_ref(rctx);
+	if (rctx->alpha_ref_dirty)
+		r600_update_alpha_ref(rctx);
 
 	mask = 0;
 	for (int i = 0; i < rctx->framebuffer.nr_cbufs; i++) {