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authorMarek Olšák <[email protected]>2014-12-29 14:45:49 +0100
committerMarek Olšák <[email protected]>2015-01-07 12:06:43 +0100
commitedf18da85dd3b1865c4faaba650a8fa371b7103c (patch)
tree5cf04bf87559911e77dd5c57093bb2d64503e390 /src/gallium/drivers/r600
parent73c2b0d18c51459697d8ec194ecfc4438c98c139 (diff)
radeonsi: only flush the right set of caches for CP DMA operations
That's either framebuffer caches or caches for shader resources. The motivation is that framebuffer caches need to be flushed very rarely here. Reviewed-by: Michel Dänzer <[email protected]>
Diffstat (limited to 'src/gallium/drivers/r600')
-rw-r--r--src/gallium/drivers/r600/r600_blit.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c
index bdc5f9f9bc2..01262a59e90 100644
--- a/src/gallium/drivers/r600/r600_blit.c
+++ b/src/gallium/drivers/r600/r600_blit.c
@@ -565,7 +565,8 @@ static void r600_copy_global_buffer(struct pipe_context *ctx,
}
static void r600_clear_buffer(struct pipe_context *ctx, struct pipe_resource *dst,
- unsigned offset, unsigned size, unsigned value)
+ unsigned offset, unsigned size, unsigned value,
+ bool is_framebuffer)
{
struct r600_context *rctx = (struct r600_context*)ctx;