gallium: introduce get_shader_param (ALL DRIVERS CHANGED) (v3)

Changes in v3:
- Also change trace, which I forgot about

Changes in v2:
- No longer adds tessellation shaders

Currently each shader cap has FS and VS versions.

However, we want a version of them for geometry, tessellation control,
and tessellation evaluation shaders, and want to be able to easily
query a given cap type for a given shader stage.

Since having 5 duplicates of each shader cap is unmanageable, add
a new get_shader_param function that takes both a shader cap from a
new enum and a shader stage.

Drivers with non-unified shaders will first switch on the shader
and, within each case, switch on the cap.

Drivers with unified shaders instead first check whether the shader
is supported, and then switch on the cap.

MAX_CONST_BUFFERS is now per-stage.
The geometry shader cap is removed in favor of checking whether the
limit of geometry shader instructions is greater than 0, which is also
used for tessellation shaders.

WARNING: all drivers changed and compiled but only nvfx tested

1 files changed, 48 insertions, 45 deletions

diff --git a/src/gallium/drivers/r600/r600_screen.c b/src/gallium/drivers/r600/r600_screen.c
index bb215a33670..19d1005e771 100644
--- a/src/gallium/drivers/r600/r600_screen.c
+++ b/src/gallium/drivers/r600/r600_screen.c
@@ -76,10 +76,8 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 
 	/* Unsupported features (boolean caps). */
 	case PIPE_CAP_TIMER_QUERY:
-	case PIPE_CAP_TGSI_CONT_SUPPORTED:
 	case PIPE_CAP_STREAM_OUTPUT:
 	case PIPE_CAP_INDEP_BLEND_FUNC: /* FIXME allow this */
-	case PIPE_CAP_GEOMETRY_SHADER4:
 		return 0;
 
 	/* Texturing. */
@@ -106,55 +104,59 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 	case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 	case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 		return 0;
-
-	/* Shader limits. */
-	case PIPE_CAP_MAX_VS_INSTRUCTIONS:
-		return 16384;  //max native instructions, not greater than max instructions
-	case PIPE_CAP_MAX_VS_ALU_INSTRUCTIONS:
-	case PIPE_CAP_MAX_VS_TEX_INSTRUCTIONS:
-	case PIPE_CAP_MAX_VS_TEX_INDIRECTIONS:
-		return 16384;
-	case PIPE_CAP_MAX_FS_INSTRUCTIONS:
-		return 16384; //max program native instructions
-	case PIPE_CAP_MAX_FS_ALU_INSTRUCTIONS:
-		return 16384; //max program native ALU instructions
-	case PIPE_CAP_MAX_FS_TEX_INSTRUCTIONS:
-		return 16384; //max program native texture instructions
-	case PIPE_CAP_MAX_FS_TEX_INDIRECTIONS:
-		return 2048; //max program native texture indirections
-	case PIPE_CAP_MAX_VS_CONTROL_FLOW_DEPTH:
-	case PIPE_CAP_MAX_FS_CONTROL_FLOW_DEPTH:
-		return 8; /* FIXME */
-	case PIPE_CAP_MAX_VS_INPUTS:
-		return 16; //max native attributes
-	case PIPE_CAP_MAX_FS_INPUTS:
-		return 10; //max native attributes
-	case PIPE_CAP_MAX_VS_TEMPS:
-		return 256; //max native temporaries
-	case PIPE_CAP_MAX_FS_TEMPS:
-		return 256; //max native temporaries
-	case PIPE_CAP_MAX_VS_ADDRS:
-	case PIPE_CAP_MAX_FS_ADDRS:
-		return 1; //max native address registers/* FIXME Isn't this equal to TEMPS? */
-	case PIPE_CAP_MAX_VS_CONSTS:
-		return 256; //max native parameters
-	case PIPE_CAP_MAX_FS_CONSTS:
-		return 256; //max program native parameters
-	case PIPE_CAP_MAX_CONST_BUFFERS:
-		return 1;
-	case PIPE_CAP_MAX_CONST_BUFFER_SIZE: /* in bytes */
-		return 4096;
-	case PIPE_CAP_MAX_PREDICATE_REGISTERS:
-	case PIPE_CAP_MAX_VS_PREDS:
-	case PIPE_CAP_MAX_FS_PREDS:
-		return 0; /* FIXME */
-
 	default:
 		R600_ERR("r600: unknown param %d\n", param);
 		return 0;
 	}
 }
 
+static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
+{
+	switch(shader)
+	{
+	case PIPE_SHADER_FRAGMENT:
+	case PIPE_SHADER_VERTEX:
+		break;
+	case PIPE_SHADER_GEOMETRY:
+		/* TODO: support and enable geometry programs */
+		return 0;
+	default:
+		/* TODO: support tessellation on Evergreen */
+		return 0;
+	}
+
+	/* TODO: all these should be fixed, since r600 surely supports much more! */
+        switch (param) {
+        case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
+        case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
+        case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
+        case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
+                return 16384;
+        case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
+                return 8; /* FIXME */
+        case PIPE_SHADER_CAP_MAX_INPUTS:
+		if(shader == PIPE_SHADER_FRAGMENT)
+			return 10;
+		else
+			return 16;
+        case PIPE_SHADER_CAP_MAX_TEMPS:
+                return 256; //max native temporaries
+        case PIPE_SHADER_CAP_MAX_ADDRS:
+                return 1; //max native address registers/* FIXME Isn't this equal to TEMPS? */
+        case PIPE_SHADER_CAP_MAX_CONSTS:
+                return 256; //max native parameters
+        case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
+                return 1;
+        case PIPE_SHADER_CAP_MAX_PREDS:
+                return 0; /* FIXME */
+        case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
+                /* TODO: support this! */
+                return 0;
+        default:
+                return 0;
+        }
+}
+
 static float r600_get_paramf(struct pipe_screen* pscreen, enum pipe_cap param)
 {
 	switch (param) {
@@ -281,6 +283,7 @@ struct pipe_screen *r600_screen_create(struct radeon *rw)
 	rscreen->screen.get_name = r600_get_name;
 	rscreen->screen.get_vendor = r600_get_vendor;
 	rscreen->screen.get_param = r600_get_param;
+	rscreen->screen.get_shader_param = r600_get_shader_param;
 	rscreen->screen.get_paramf = r600_get_paramf;
 	rscreen->screen.is_format_supported = r600_is_format_supported;
 	rscreen->screen.context_create = r600_create_context;