r600g: fix texture bos and avoid doing depth blit on evergreen

since the depth blit code is hardcoded hex yay \o/

2 files changed, 4 insertions, 11 deletions

diff --git a/src/gallium/drivers/r600/eg_hw_states.c b/src/gallium/drivers/r600/eg_hw_states.c
index ae03994e8b3..a58adc6bab4 100644
--- a/src/gallium/drivers/r600/eg_hw_states.c
+++ b/src/gallium/drivers/r600/eg_hw_states.c
@@ -1065,21 +1065,13 @@ static void eg_texture_state_cb(struct r600_screen *rscreen, struct r600_resourc
 	swap = r600_translate_colorswap(rtexture->resource.base.b.format);
 	if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
 		rstate->bo[0] = radeon_bo_incref(rscreen->rw, rtexture->uncompressed);
-		rstate->bo[1] = radeon_bo_incref(rscreen->rw, rtexture->uncompressed);
-		rstate->bo[2] = radeon_bo_incref(rscreen->rw, rtexture->uncompressed);
 		rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
-		rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
-		rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
-		rstate->nbo = 3;
+		rstate->nbo = 1;
 		color_info = 0;
 	} else {
 		rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
-		rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
-		rstate->bo[2] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
 		rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
-		rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
-		rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
-		rstate->nbo = 3;
+		rstate->nbo = 1;
 		color_info = S_028C70_SOURCE_FORMAT(1);
 	}
 	color_info |= S_028C70_FORMAT(format) |
diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
index 158ae227b1d..80cfa36ac01 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -314,6 +314,7 @@ void r600_texture_transfer_destroy(struct pipe_context *ctx,
 void* r600_texture_transfer_map(struct pipe_context *ctx,
 				struct pipe_transfer* transfer)
 {
+	struct r600_screen *rscreen = r600_screen(ctx->screen);
 	struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 	struct radeon_bo *bo;
 	enum pipe_format format = transfer->resource->format;
@@ -328,7 +329,7 @@ void* r600_texture_transfer_map(struct pipe_context *ctx,
 		bo = ((struct r600_resource *)rtransfer->linear_texture)->bo;
 	} else {
 		rtex = (struct r600_resource_texture*)transfer->resource;
-		if (rtex->depth) {
+		if (rtex->depth && rscreen->chip_class != EVERGREEN) {
 			r = r600_texture_from_depth(ctx, rtex, transfer->sr.level);
 			if (r) {
 				return NULL;