r600g: improve bo flushing

Flush read cache before writting register. Track flushing inside
of a same cs and avoid reflushing same bo if not necessary. Allmost
properly force flush if bo rendered too and then use as a texture
in same cs (missing pipeline flush dunno if it's needed or not).

Signed-off-by: Jerome Glisse <[email protected]>

1 files changed, 3 insertions, 0 deletions

diff --git a/src/gallium/drivers/r600/r600.h b/src/gallium/drivers/r600/r600.h
index 8a2e5c514d4..59a255d2fae 100644
--- a/src/gallium/drivers/r600/r600.h
+++ b/src/gallium/drivers/r600/r600.h
@@ -154,6 +154,8 @@ static inline void r600_pipe_state_add_reg(struct r600_pipe_state *state,
 struct r600_block_reloc {
 	struct r600_bo	*bo;
 	unsigned		nreloc;
+	unsigned		flush_flags;
+	unsigned		flush_mask;
 	unsigned		bo_pm4_index[R600_BLOCK_MAX_BO];
 };
 
@@ -161,6 +163,7 @@ struct r600_block {
 	unsigned		status;
 	unsigned		start_offset;
 	unsigned		pm4_ndwords;
+	unsigned		pm4_flush_ndwords;
 	unsigned		nbo;
 	unsigned		nreg;
 	u32			*reg;