diff options
| author | Jerome Glisse <[email protected]> | 2010-07-21 17:03:38 -0400 |
|---|---|---|
| committer | Jerome Glisse <[email protected]> | 2010-07-21 17:05:37 -0400 |
| commit | 0bca8fbfdab4a19ddbb4f33aaef372246a5d2cc2 (patch) | |
| tree | b3de97a4664ffaa0b3090545aa40c44e0adfb95d /src/gallium/drivers/r600/r700_sq.h | |
| parent | 4b2820534e3635a8ecd047f1e0139834e0a67d02 (diff) | |
r600g: add support for all R6XX/R7XX asic
This configure some of the value properly based on
asic so others asic than RV710 works too.
Signed-off-by: Jerome Glisse <[email protected]>
Diffstat (limited to 'src/gallium/drivers/r600/r700_sq.h')
| -rw-r--r-- | src/gallium/drivers/r600/r700_sq.h | 22 |
1 files changed, 0 insertions, 22 deletions
diff --git a/src/gallium/drivers/r600/r700_sq.h b/src/gallium/drivers/r600/r700_sq.h index 8266af6d1fc..9a117aeb1d3 100644 --- a/src/gallium/drivers/r600/r700_sq.h +++ b/src/gallium/drivers/r600/r700_sq.h @@ -583,27 +583,5 @@ #define S_SQ_TEX_WORD2_SRC_SEL_W(x) (((x) & 0x7) << 29) #define G_SQ_TEX_WORD2_SRC_SEL_W(x) (((x) >> 29) & 0x7) #define C_SQ_TEX_WORD2_SRC_SEL_W 0x1FFFFFFF -#define P_SQ_ALU_WORD1_OP2_V2 -#define S_SQ_ALU_WORD1_OP2_V2_SRC0_ABS(x) (((x) & 0x1) << 0) -#define G_SQ_ALU_WORD1_OP2_V2_SRC0_ABS(x) (((x) >> 0) & 0x1) -#define C_SQ_ALU_WORD1_OP2_V2_SRC0_ABS 0xFFFFFFFE -#define S_SQ_ALU_WORD1_OP2_V2_SRC1_ABS(x) (((x) & 0x1) << 1) -#define G_SQ_ALU_WORD1_OP2_V2_SRC1_ABS(x) (((x) >> 1) & 0x1) -#define C_SQ_ALU_WORD1_OP2_V2_SRC1_ABS 0xFFFFFFFD -#define S_SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK(x) (((x) & 0x1) << 2) -#define G_SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK(x) (((x) >> 2) & 0x1) -#define C_SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK 0xFFFFFFFB -#define S_SQ_ALU_WORD1_OP2_V2_UPDATE_PRED(x) (((x) & 0x1) << 3) -#define G_SQ_ALU_WORD1_OP2_V2_UPDATE_PRED(x) (((x) >> 3) & 0x1) -#define C_SQ_ALU_WORD1_OP2_V2_UPDATE_PRED 0xFFFFFFF7 -#define S_SQ_ALU_WORD1_OP2_V2_WRITE_MASK(x) (((x) & 0x1) << 4) -#define G_SQ_ALU_WORD1_OP2_V2_WRITE_MASK(x) (((x) >> 4) & 0x1) -#define C_SQ_ALU_WORD1_OP2_V2_WRITE_MASK 0xFFFFFFEF -#define S_SQ_ALU_WORD1_OP2_V2_OMOD(x) (((x) & 0x3) << 5) -#define G_SQ_ALU_WORD1_OP2_V2_OMOD(x) (((x) >> 5) & 0x3) -#define C_SQ_ALU_WORD1_OP2_V2_OMOD 0xFFFFFF9F -#define S_SQ_ALU_WORD1_OP2_V2_ALU_INST(x) (((x) & 0x7FF) << 7) -#define G_SQ_ALU_WORD1_OP2_V2_ALU_INST(x) (((x) >> 7) & 0x7FF) -#define C_SQ_ALU_WORD1_OP2_V2_ALU_INST 0xFFFC007F #endif |