diff options
| author | Vadim Girlin <[email protected]> | 2013-02-01 11:45:35 +0400 |
|---|---|---|
| committer | Vadim Girlin <[email protected]> | 2013-02-01 12:08:42 +0400 |
| commit | 022122ee63b8a00afc23eaa347df934a79fb1d4c (patch) | |
| tree | b014eeb8150f2425140973923f9a7d4052e52ec5 /src/gallium/drivers/r600/r700_asm.c | |
| parent | b68a3b865be2dbd002f1fb8fc3eba20c4293a5bd (diff) | |
r600g: use tables with ISA info v3
v3: added some flags including condition codes for ALU,
fixed issue with CF reverse lookup (overlapping ranges of CF_ALU_xxx
and other CF instructions)
rebased on current master
Signed-off-by: Vadim Girlin <[email protected]>
Diffstat (limited to 'src/gallium/drivers/r600/r700_asm.c')
| -rw-r--r-- | src/gallium/drivers/r600/r700_asm.c | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/src/gallium/drivers/r600/r700_asm.c b/src/gallium/drivers/r600/r700_asm.c index 47b4f91ee1d..4a9fa3612e1 100644 --- a/src/gallium/drivers/r600/r700_asm.c +++ b/src/gallium/drivers/r600/r700_asm.c @@ -27,7 +27,7 @@ void r700_bytecode_cf_vtx_build(uint32_t *bytecode, const struct r600_bytecode_c { unsigned count = (cf->ndw / 4) - 1; *bytecode++ = S_SQ_CF_WORD0_ADDR(cf->addr >> 1); - *bytecode++ = cf->inst | + *bytecode++ = S_SQ_CF_WORD1_CF_INST(r600_isa_cf_opcode(ISA_CC_R700, cf->op)) | S_SQ_CF_WORD1_BARRIER(1) | S_SQ_CF_WORD1_COUNT(count) | S_SQ_CF_WORD1_COUNT_3(count >> 3); @@ -56,7 +56,7 @@ int r700_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu * S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) | S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) | S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) | - S_SQ_ALU_WORD1_OP3_ALU_INST(alu->inst) | + S_SQ_ALU_WORD1_OP3_ALU_INST(r600_isa_alu_opcode(bc->isa->hw_class, alu->op)) | S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle); } else { bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) | @@ -67,7 +67,7 @@ int r700_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu * S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) | S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) | S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) | - S_SQ_ALU_WORD1_OP2_ALU_INST(alu->inst) | + S_SQ_ALU_WORD1_OP2_ALU_INST(r600_isa_alu_opcode(bc->isa->hw_class, alu->op)) | S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) | S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->execute_mask) | S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->update_pred); @@ -75,7 +75,8 @@ int r700_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu * return 0; } -void r700_bytecode_alu_read(struct r600_bytecode_alu *alu, uint32_t word0, uint32_t word1) +void r700_bytecode_alu_read(struct r600_bytecode *bc, + struct r600_bytecode_alu *alu, uint32_t word0, uint32_t word1) { /* WORD0 */ alu->src[0].sel = G_SQ_ALU_WORD0_SRC0_SEL(word0); @@ -105,13 +106,15 @@ void r700_bytecode_alu_read(struct r600_bytecode_alu *alu, uint32_t word0, uint3 alu->src[2].rel = G_SQ_ALU_WORD1_OP3_SRC2_REL(word1); alu->src[2].chan = G_SQ_ALU_WORD1_OP3_SRC2_CHAN(word1); alu->src[2].neg = G_SQ_ALU_WORD1_OP3_SRC2_NEG(word1); - alu->inst = G_SQ_ALU_WORD1_OP3_ALU_INST(word1); + alu->op = r600_isa_alu_by_opcode(bc->isa, + G_SQ_ALU_WORD1_OP3_ALU_INST(word1), 1); } else /*ALU_DWORD1_OP2*/ { alu->src[0].abs = G_SQ_ALU_WORD1_OP2_SRC0_ABS(word1); alu->src[1].abs = G_SQ_ALU_WORD1_OP2_SRC1_ABS(word1); - alu->inst = G_SQ_ALU_WORD1_OP2_ALU_INST(word1); + alu->op = r600_isa_alu_by_opcode(bc->isa, + G_SQ_ALU_WORD1_OP2_ALU_INST(word1), 0); alu->omod = G_SQ_ALU_WORD1_OP2_OMOD(word1); alu->dst.write = G_SQ_ALU_WORD1_OP2_WRITE_MASK(word1); alu->update_pred = G_SQ_ALU_WORD1_OP2_UPDATE_PRED(word1); |