diff options
| author | Glenn Kennard <[email protected]> | 2017-03-05 18:26:49 +0100 |
|---|---|---|
| committer | Dave Airlie <[email protected]> | 2018-02-09 09:52:48 +1000 |
| commit | 9c48a139b08f223f4ac6e218d19b356bf4a41463 (patch) | |
| tree | e4304278ae6576589490eb03a9112d5e9de293e0 /src/gallium/drivers/r600/r700_asm.c | |
| parent | 2a891ed19065dac89e8639800d3c63274d19a97a (diff) | |
r600g: Support emitting scratch ops
Signed-off-by: Glenn Kennard <[email protected]>
Reviewed-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/gallium/drivers/r600/r700_asm.c')
| -rw-r--r-- | src/gallium/drivers/r600/r700_asm.c | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/src/gallium/drivers/r600/r700_asm.c b/src/gallium/drivers/r600/r700_asm.c index 395059cfeaa..adf5445a2f5 100644 --- a/src/gallium/drivers/r600/r700_asm.c +++ b/src/gallium/drivers/r600/r700_asm.c @@ -124,3 +124,42 @@ void r700_bytecode_alu_read(struct r600_bytecode *bc, G_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(word1); } } + +int r700_bytecode_fetch_mem_build(struct r600_bytecode *bc, struct r600_bytecode_vtx *mem, unsigned id) +{ + unsigned opcode = r600_isa_fetch_opcode(bc->isa->hw_class, mem->op) >> 8; + + bc->bytecode[id++] = S_SQ_MEM_RD_WORD0_MEM_INST(2) | + S_SQ_MEM_RD_WORD0_ELEM_SIZE(mem->elem_size) | + S_SQ_MEM_RD_WORD0_FETCH_WHOLE_QUAD(0) | + S_SQ_MEM_RD_WORD0_MEM_OP(opcode) | + S_SQ_MEM_RD_WORD0_UNCACHED(mem->uncached) | + S_SQ_MEM_RD_WORD0_INDEXED(mem->indexed) | + S_SQ_MEM_RD_WORD0_SRC_SEL_Y(mem->src_sel_y) | + S_SQ_MEM_RD_WORD0_SRC_GPR(mem->src_gpr) | + S_SQ_MEM_RD_WORD0_SRC_REL(mem->src_rel) | + S_SQ_MEM_RD_WORD0_SRC_SEL_X(mem->src_sel_x) | + S_SQ_MEM_RD_WORD0_BURST_COUNT(mem->burst_count) | + S_SQ_MEM_RD_WORD0_LDS_REQ(0) | + S_SQ_MEM_RD_WORD0_COALESCED_READ(0); + + bc->bytecode[id++] = S_SQ_MEM_RD_WORD1_DST_GPR(mem->dst_gpr) | + S_SQ_MEM_RD_WORD1_DST_REL(mem->dst_rel) | + S_SQ_MEM_RD_WORD1_DST_SEL_X(mem->dst_sel_x) | + S_SQ_MEM_RD_WORD1_DST_SEL_Y(mem->dst_sel_y) | + S_SQ_MEM_RD_WORD1_DST_SEL_W(mem->dst_sel_w) | + S_SQ_MEM_RD_WORD1_DST_SEL_Z(mem->dst_sel_z) | + S_SQ_MEM_RD_WORD1_DATA_FORMAT(mem->data_format) | + S_SQ_MEM_RD_WORD1_NUM_FORMAT_ALL(mem->num_format_all) | + S_SQ_MEM_RD_WORD1_FORMAT_COMP_ALL(mem->format_comp_all) | + S_SQ_MEM_RD_WORD1_SRF_MODE_ALL(mem->srf_mode_all); + + bc->bytecode[id++] = S_SQ_MEM_RD_WORD2_ARRAY_BASE(mem->array_base) | + S_SQ_MEM_RD_WORD2_ENDIAN_SWAP(0) | + S_SQ_MEM_RD_WORD2_ARRAY_SIZE(mem->array_size); + + + bc->bytecode[id++] = 0; /* MEM ops are 4 word aligned */ + + return 0; +} |