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authorGert Wollny <[email protected]>2017-11-17 12:13:40 +0100
committerDave Airlie <[email protected]>2017-11-22 22:39:42 +0000
commit1d076aafbc05b0af299826ac0ee63b2fb28e944a (patch)
treec57ea11f462f5daa4923372fa0e2774af1471c45 /src/gallium/drivers/r600/r700_asm.c
parentc2dad6ca0a120ae133fe32925c20e1e9856132d9 (diff)
r600: Emit EOP for more CF instruction types
So far on pre-cayman chipsets the CF instructions CF_OP_LOOP_END, CF_OP_CALL_FS, CF_OP_POP, and CF_OP_GDS an extra CF_NOP instruction was added to add the EOP flag, even though this is not actually needed, because all these instrutions support the EOP flag. This patch removes the fixup code, adds setting the EOP flag for the according instructions as well as others like CF_OP_TEX and CF_OP_VTX, and adds writing out EOP for this type of instruction in the disassembler. This also fixes a bug where shaders were created that didn't actually have the EOP flag set in the last CF instruction, which might have resulted in GPU lockups. [airlied: cleaned up a little] Signed-off-by: Gert Wollny <[email protected]> Cc: <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/gallium/drivers/r600/r700_asm.c')
-rw-r--r--src/gallium/drivers/r600/r700_asm.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/gallium/drivers/r600/r700_asm.c b/src/gallium/drivers/r600/r700_asm.c
index 04f8c6288f0..395059cfeaa 100644
--- a/src/gallium/drivers/r600/r700_asm.c
+++ b/src/gallium/drivers/r600/r700_asm.c
@@ -30,7 +30,8 @@ void r700_bytecode_cf_vtx_build(uint32_t *bytecode, const struct r600_bytecode_c
*bytecode++ = S_SQ_CF_WORD1_CF_INST(r600_isa_cf_opcode(ISA_CC_R700, cf->op)) |
S_SQ_CF_WORD1_BARRIER(1) |
S_SQ_CF_WORD1_COUNT(count) |
- S_SQ_CF_WORD1_COUNT_3(count >> 3);
+ S_SQ_CF_WORD1_COUNT_3(count >> 3)|
+ S_SQ_CF_WORD1_END_OF_PROGRAM(cf->end_of_program);
}
int r700_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id)