diff options
author | Marek Olšák <[email protected]> | 2012-10-05 19:39:14 +0200 |
---|---|---|
committer | Marek Olšák <[email protected]> | 2012-10-10 00:16:58 +0200 |
commit | 711f3bae9d8bde9750448c23fde4a15efbcfacb5 (patch) | |
tree | d6391f98d67f8b6b22a73b93e05a24af50e3440c /src/gallium/drivers/r600/r600_state.c | |
parent | 9a683d1bd82a2252df5a3841dc9108ba767a023a (diff) |
r600g: atomize rasterizer state
Reviewed-by: Jerome Glisse <[email protected]>
Diffstat (limited to 'src/gallium/drivers/r600/r600_state.c')
-rw-r--r-- | src/gallium/drivers/r600/r600_state.c | 123 |
1 files changed, 55 insertions, 68 deletions
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c index d7e04305f7d..06f76feb6fb 100644 --- a/src/gallium/drivers/r600/r600_state.c +++ b/src/gallium/drivers/r600/r600_state.c @@ -844,24 +844,16 @@ static void *r600_create_rs_state(struct pipe_context *ctx, const struct pipe_rasterizer_state *state) { struct r600_context *rctx = (struct r600_context *)ctx; - struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer); - struct r600_pipe_state *rstate; - unsigned tmp; - unsigned prov_vtx = 1, polygon_dual_mode; - unsigned sc_mode_cntl; + unsigned tmp, sc_mode_cntl, spi_interp; float psize_min, psize_max; + struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state); if (rs == NULL) { return NULL; } - polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL || - state->fill_back != PIPE_POLYGON_MODE_FILL); - - if (state->flatshade_first) - prov_vtx = 0; + r600_init_command_buffer(&rs->buffer, 30); - rstate = &rs->rstate; rs->flatshade = state->flatshade; rs->sprite_coord_enable = state->sprite_coord_enable; rs->two_side = state->light_twoside; @@ -881,24 +873,6 @@ static void *r600_create_rs_state(struct pipe_context *ctx, rs->offset_scale = state->offset_scale * 12.0f; rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri; - rstate->id = R600_PIPE_STATE_RASTERIZER; - tmp = S_0286D4_FLAT_SHADE_ENA(1); - if (state->sprite_coord_enable) { - tmp |= S_0286D4_PNT_SPRITE_ENA(1) | - S_0286D4_PNT_SPRITE_OVRD_X(2) | - S_0286D4_PNT_SPRITE_OVRD_Y(3) | - S_0286D4_PNT_SPRITE_OVRD_Z(0) | - S_0286D4_PNT_SPRITE_OVRD_W(1); - if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) { - tmp |= S_0286D4_PNT_SPRITE_TOP_1(1); - } - } - r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp); - - /* point size 12.4 fixed point */ - tmp = r600_pack_float_12p4(state->point_size/2); - r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp)); - if (state->point_size_per_vertex) { psize_min = util_get_min_point_size(state); psize_max = 8192; @@ -907,50 +881,62 @@ static void *r600_create_rs_state(struct pipe_context *ctx, psize_min = state->point_size; psize_max = state->point_size; } - /* Divide by two, because 0.5 = 1 pixel. */ - r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, - S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) | - S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2))); - - tmp = r600_pack_float_12p4(state->line_width/2); - r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp)); + sc_mode_cntl = S_028A4C_MSAA_ENABLE(state->multisample) | + S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable) | + S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1); if (rctx->chip_class >= R700) { - sc_mode_cntl = - S_028A4C_MSAA_ENABLE(state->multisample) | - S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) | - S_028A4C_FORCE_EOV_REZ_ENABLE(1) | - S_028A4C_R700_ZMM_LINE_OFFSET(1) | - S_028A4C_R700_VPORT_SCISSOR_ENABLE(state->scissor); + sc_mode_cntl |= S_028A4C_FORCE_EOV_REZ_ENABLE(1) | + S_028A4C_R700_ZMM_LINE_OFFSET(1) | + S_028A4C_R700_VPORT_SCISSOR_ENABLE(state->scissor); } else { - sc_mode_cntl = - S_028A4C_MSAA_ENABLE(state->multisample) | - S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) | - S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1); + sc_mode_cntl |= S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1); rs->scissor_enable = state->scissor; } - sc_mode_cntl |= S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable); - - r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl); - - r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL, - S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules) | - S_028C08_QUANT_MODE(V_028C08_X_1_256TH)); - - r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp)); - r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL, - S_028814_PROVOKING_VTX_LAST(prov_vtx) | - S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) | - S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) | - S_028814_FACE(!state->front_ccw) | - S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) | - S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) | - S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) | - S_028814_POLY_MODE(polygon_dual_mode) | - S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) | - S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back))); - r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard)); - return rstate; + + spi_interp = S_0286D4_FLAT_SHADE_ENA(1); + if (state->sprite_coord_enable) { + spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) | + S_0286D4_PNT_SPRITE_OVRD_X(2) | + S_0286D4_PNT_SPRITE_OVRD_Y(3) | + S_0286D4_PNT_SPRITE_OVRD_Z(0) | + S_0286D4_PNT_SPRITE_OVRD_W(1); + if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) { + spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1); + } + } + + r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3); + /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel. */ + tmp = r600_pack_float_12p4(state->point_size/2); + r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */ + S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp)); + r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */ + S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) | + S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2))); + r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */ + S_028A08_WIDTH(r600_pack_float_12p4(state->line_width/2))); + + r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp); + r600_store_context_reg(&rs->buffer, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl); + r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL, + S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules) | + S_028C08_QUANT_MODE(V_028C08_X_1_256TH)); + r600_store_context_reg(&rs->buffer, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp)); + r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL, + S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) | + S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) | + S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) | + S_028814_FACE(!state->front_ccw) | + S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) | + S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) | + S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) | + S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL || + state->fill_back != PIPE_POLYGON_MODE_FILL) | + S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) | + S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back))); + r600_store_context_reg(&rs->buffer, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard)); + return rs; } static void *r600_create_sampler_state(struct pipe_context *ctx, @@ -2179,6 +2165,7 @@ void r600_init_state_functions(struct r600_context *rctx) r600_init_atom(rctx, &rctx->clip_state.atom, id++, r600_emit_clip_state, 26); r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, r600_emit_db_misc_state, 4); r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, r600_emit_polygon_offset, 6); + r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0); r600_init_atom(rctx, &rctx->scissor.atom, id++, r600_emit_scissor_state, 4); r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4); r600_init_atom(rctx, &rctx->viewport.atom, id++, r600_emit_viewport_state, 8); |