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authorGrazvydas Ignotas <[email protected]>2015-12-22 04:12:07 +0200
committerNicolai Hähnle <[email protected]>2015-12-29 09:05:55 -0500
commitda0e216e069bd064199ed04b52de6fb23d810806 (patch)
tree2512f42acc3d6e68aa394774bab1fd432cf2c4af /src/gallium/drivers/r600/r600_state.c
parentdfce9759abbc13f7f735ac4bf3f1a19737624ae6 (diff)
r600: fix constant buffer size programming
When buffer size is less than 16, zero ends up being programmed as size, which prevents the hardware from fetching the correct values. Fix it by combining shift and align so that the value is always rounded up. Cc: "11.1 11.0 10.6" <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92229 Signed-off-by: Grazvydas Ignotas <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src/gallium/drivers/r600/r600_state.c')
-rw-r--r--src/gallium/drivers/r600/r600_state.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index e7ffe0dab1c..43b80742cb5 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -1768,7 +1768,7 @@ static void r600_emit_constant_buffers(struct r600_context *rctx,
if (!gs_ring_buffer) {
radeon_set_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
- ALIGN_DIVUP(cb->buffer_size >> 4, 16));
+ ALIGN_DIVUP(cb->buffer_size, 256));
radeon_set_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
}