diff options
| author | Eric Anholt <[email protected]> | 2014-11-12 13:13:59 -0800 |
|---|---|---|
| committer | Eric Anholt <[email protected]> | 2014-11-24 14:56:22 -0800 |
| commit | d4864cdf15ccd30f0e82d07fd0e9db8a0c115cda (patch) | |
| tree | fddfda125d068bb4b451ca411fe9fc6b130a9d62 /src/gallium/drivers/r600/r600_shader.c | |
| parent | 7361d5ba63dda35683569e76caa33f886304958f (diff) | |
gallium: Drop the NRM and NRM4 opcodes.
They weren't generated in tree, and as far as I know all hardware had to
lower it to a DP, RSQ, MUL.
Reviewed-by: Jose Fonseca <[email protected]>
Diffstat (limited to 'src/gallium/drivers/r600/r600_shader.c')
| -rw-r--r-- | src/gallium/drivers/r600/r600_shader.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c index 29d27ce821c..10a5ca0b1ae 100644 --- a/src/gallium/drivers/r600/r600_shader.c +++ b/src/gallium/drivers/r600/r600_shader.c @@ -7257,7 +7257,7 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = { {TGSI_OPCODE_CMP, 0, ALU_OP0_NOP, tgsi_cmp}, {TGSI_OPCODE_SCS, 0, ALU_OP0_NOP, tgsi_scs}, {TGSI_OPCODE_TXB, 0, FETCH_OP_SAMPLE_LB, tgsi_tex}, - {TGSI_OPCODE_NRM, 0, ALU_OP0_NOP, tgsi_unsupported}, + {69, 0, ALU_OP0_NOP, tgsi_unsupported}, {TGSI_OPCODE_DIV, 0, ALU_OP0_NOP, tgsi_unsupported}, {TGSI_OPCODE_DP2, 0, ALU_OP2_DOT4, tgsi_dp}, {TGSI_OPCODE_TXL, 0, FETCH_OP_SAMPLE_L, tgsi_tex}, @@ -7300,7 +7300,7 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = { {TGSI_OPCODE_FSGE, 0, ALU_OP2_SETGE_DX10, tgsi_op2}, {TGSI_OPCODE_FSLT, 0, ALU_OP2_SETGT_DX10, tgsi_op2_swap}, {TGSI_OPCODE_FSNE, 0, ALU_OP2_SETNE_DX10, tgsi_op2_swap}, - {TGSI_OPCODE_NRM4, 0, ALU_OP0_NOP, tgsi_unsupported}, + {112, 0, ALU_OP0_NOP, tgsi_unsupported}, {TGSI_OPCODE_CALLNZ, 0, ALU_OP0_NOP, tgsi_unsupported}, {114, 0, ALU_OP0_NOP, tgsi_unsupported}, {TGSI_OPCODE_BREAKC, 0, ALU_OP0_NOP, tgsi_loop_breakc}, @@ -7456,7 +7456,7 @@ static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = { {TGSI_OPCODE_CMP, 0, ALU_OP0_NOP, tgsi_cmp}, {TGSI_OPCODE_SCS, 0, ALU_OP0_NOP, tgsi_scs}, {TGSI_OPCODE_TXB, 0, FETCH_OP_SAMPLE_LB, tgsi_tex}, - {TGSI_OPCODE_NRM, 0, ALU_OP0_NOP, tgsi_unsupported}, + {69, 0, ALU_OP0_NOP, tgsi_unsupported}, {TGSI_OPCODE_DIV, 0, ALU_OP0_NOP, tgsi_unsupported}, {TGSI_OPCODE_DP2, 0, ALU_OP2_DOT4, tgsi_dp}, {TGSI_OPCODE_TXL, 0, FETCH_OP_SAMPLE_L, tgsi_tex}, @@ -7499,7 +7499,7 @@ static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = { {TGSI_OPCODE_FSGE, 0, ALU_OP2_SETGE_DX10, tgsi_op2}, {TGSI_OPCODE_FSLT, 0, ALU_OP2_SETGT_DX10, tgsi_op2_swap}, {TGSI_OPCODE_FSNE, 0, ALU_OP2_SETNE_DX10, tgsi_op2_swap}, - {TGSI_OPCODE_NRM4, 0, ALU_OP0_NOP, tgsi_unsupported}, + {112, 0, ALU_OP0_NOP, tgsi_unsupported}, {TGSI_OPCODE_CALLNZ, 0, ALU_OP0_NOP, tgsi_unsupported}, {114, 0, ALU_OP0_NOP, tgsi_unsupported}, {TGSI_OPCODE_BREAKC, 0, ALU_OP0_NOP, tgsi_unsupported}, @@ -7655,7 +7655,7 @@ static struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = { {TGSI_OPCODE_CMP, 0, ALU_OP0_NOP, tgsi_cmp}, {TGSI_OPCODE_SCS, 0, ALU_OP0_NOP, tgsi_scs}, {TGSI_OPCODE_TXB, 0, FETCH_OP_SAMPLE_LB, tgsi_tex}, - {TGSI_OPCODE_NRM, 0, ALU_OP0_NOP, tgsi_unsupported}, + {69, 0, ALU_OP0_NOP, tgsi_unsupported}, {TGSI_OPCODE_DIV, 0, ALU_OP0_NOP, tgsi_unsupported}, {TGSI_OPCODE_DP2, 0, ALU_OP2_DOT4, tgsi_dp}, {TGSI_OPCODE_TXL, 0, FETCH_OP_SAMPLE_L, tgsi_tex}, @@ -7698,7 +7698,7 @@ static struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = { {TGSI_OPCODE_FSGE, 0, ALU_OP2_SETGE_DX10, tgsi_op2}, {TGSI_OPCODE_FSLT, 0, ALU_OP2_SETGT_DX10, tgsi_op2_swap}, {TGSI_OPCODE_FSNE, 0, ALU_OP2_SETNE_DX10, tgsi_op2_swap}, - {TGSI_OPCODE_NRM4, 0, ALU_OP0_NOP, tgsi_unsupported}, + {112, 0, ALU_OP0_NOP, tgsi_unsupported}, {TGSI_OPCODE_CALLNZ, 0, ALU_OP0_NOP, tgsi_unsupported}, {114, 0, ALU_OP0_NOP, tgsi_unsupported}, {TGSI_OPCODE_BREAKC, 0, ALU_OP0_NOP, tgsi_unsupported}, |