r600g: add support for common surface allocator for tiling v13

Tiled surface have all kind of alignment constraint that needs to
be met. Instead of having all this code duplicated btw ddx and
mesa use common code in libdrm_radeon this also ensure that both
ddx and mesa compute those alignment in the same way.

v2 fix evergreen
v3 fix compressed texture and workaround cube texture issue by
   disabling 2D array mode for cubemap (need to check if r7xx and
   newer are also affected by the issue)
v4 fix texture array
v5 fix evergreen and newer, split surface values computation from
   mipmap tree generation so that we can get them directly from the
   ddx
v6 final fix to evergreen tile split value
v7 fix mipmap offset to avoid to use random value, use color view
   depth view to address different layer as hardware is doing some
   magic rotation depending on the layer
v8 fix COLOR_VIEW on r6xx for linear array mode, use COLOR_VIEW on
   evergreen, align bytes per pixel to a multiple of a dword
v9 fix handling of stencil on evergreen, half fix for compressed
   texture
v10 fix evergreen compressed texture proper support for stencil
    tile split. Fix stencil issue when array mode was clear by
    the kernel, always program stencil bo. On evergreen depth
    buffer bo need to be big enough to hold depth buffer + stencil
    buffer as even with stencil disabled things get written there.
v11 rebase on top of mesa, fix pitch issue with 1d surface on evergreen,
    old ddx overestimate those. Fix linear case when pitch*height < 64.
    Fix r300g.
v12 Fix linear case when pitch*height < 64 for old path, adapt to
    libdrm API change
v13 add libdrm check

Signed-off-by: Jerome Glisse <[email protected]>

1 files changed, 1 insertions, 0 deletions

diff --git a/src/gallium/drivers/r600/r600_resource.h b/src/gallium/drivers/r600/r600_resource.h
index 1a32c056dd4..8b90b12e957 100644
--- a/src/gallium/drivers/r600/r600_resource.h
+++ b/src/gallium/drivers/r600/r600_resource.h
@@ -60,6 +60,7 @@ struct r600_resource_texture {
 	struct r600_resource_texture    *stencil; /* Stencil is in a separate buffer on Evergreen. */
 	struct r600_resource_texture	*flushed_depth_texture;
 	boolean				is_flushing_texture;
+	struct radeon_surface		surface;
 };
 
 #define R600_TEX_IS_TILED(tex, level) ((tex)->array_mode[level] != V_038000_ARRAY_LINEAR_GENERAL && (tex)->array_mode[level] != V_038000_ARRAY_LINEAR_ALIGNED)