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authorDave Airlie <[email protected]>2012-12-16 10:31:32 +0000
committerDave Airlie <[email protected]>2013-01-11 22:31:54 +0000
commitd23aa650015ec017649f5a4ce8cb12d8c314bd3a (patch)
treea76e70719be1969b929be5f96bc8f6993bfc653f /src/gallium/drivers/r600/r600_pipe.h
parent77c10225eef43eb428ebbc80f1dd426e3d33b281 (diff)
r600g: texture buffer object + glsl 1.40 enable support (v2)
This adds TBO support to r600g, and with GLSL 1.40 enabled, we now get 3.1 core profiles advertised for r600g. The r600/700 implementation is a bit different from the evergreen one, as r6/7 hw lacks vertex fetch swizzles. So we implement it by passing 5 constants per sampler to the shader, the shader uses the first 4 as masks for each component and the 5th as the alpha value to OR in. Now TXQ is also broken so we have to pass a constant for the buffer size, on evergreen we just pass this, on r6/7 we pass it as the 6th element in the const info buffer. v1.1: drop return as DDX doesn't use a texture type v2: add r600/700 support. Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/gallium/drivers/r600/r600_pipe.h')
-rw-r--r--src/gallium/drivers/r600/r600_pipe.h10
1 files changed, 9 insertions, 1 deletions
diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h
index 2dcb4734e6b..d983718b1bb 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -40,12 +40,13 @@
#define R600_TRACE_CS 0
#define R600_MAX_USER_CONST_BUFFERS 13
-#define R600_MAX_DRIVER_CONST_BUFFERS 2
+#define R600_MAX_DRIVER_CONST_BUFFERS 3
#define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
/* start driver buffers after user buffers */
#define R600_UCP_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
#define R600_TXQ_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
+#define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
#define R600_MAX_CONST_BUFFER_SIZE 4096
@@ -330,6 +331,7 @@ struct r600_samplerview_state {
uint32_t compressed_depthtex_mask; /* which textures are depth */
uint32_t compressed_colortex_mask;
boolean dirty_txq_constants;
+ boolean dirty_buffer_constants;
};
struct r600_sampler_states {
@@ -347,6 +349,8 @@ struct r600_textures_info {
/* cube array txq workaround */
uint32_t *txq_constants;
+ /* buffer related workarounds */
+ uint32_t *buffer_constants;
};
struct r600_fence {
@@ -678,6 +682,10 @@ struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
const struct pipe_surface *templ,
unsigned width, unsigned height);
+unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
+ const unsigned char *swizzle_view,
+ boolean vtx);
+
/* r600_state_common.c */
void r600_init_common_state_functions(struct r600_context *rctx);
void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom);