Revert "r600g: don't use dynamic state allocation for states"

This reverts commit 9c949d4a4dd43b7889e13bdf683bcf211f049ced.

Conflicts:

	src/gallium/drivers/r600/r600_context.h
	src/gallium/drivers/r600/r600_draw.c
	src/gallium/drivers/r600/r600_shader.c
	src/gallium/drivers/r600/r600_state.c

1 files changed, 52 insertions, 52 deletions

diff --git a/src/gallium/drivers/r600/r600_draw.c b/src/gallium/drivers/r600/r600_draw.c
index 3a54cee2d95..2420b763188 100644
--- a/src/gallium/drivers/r600/r600_draw.c
+++ b/src/gallium/drivers/r600/r600_draw.c
@@ -38,8 +38,8 @@
 
 struct r600_draw {
 	struct pipe_context	*ctx;
-	struct radeon_state	draw;
-	struct radeon_state	vgt;
+	struct radeon_state	*draw;
+	struct radeon_state	*vgt;
 	unsigned		mode;
 	unsigned		start;
 	unsigned		count;
@@ -51,7 +51,7 @@ static int r600_draw_common(struct r600_draw *draw)
 {
 	struct r600_context *rctx = r600_context(draw->ctx);
 	struct r600_screen *rscreen = rctx->screen;
-	struct radeon_state vs_resource;
+	struct radeon_state *vs_resource;
 	struct r600_resource *rbuffer;
 	unsigned i, j, offset, format, prim;
 	u32 vgt_dma_index_type, vgt_draw_initiator;
@@ -88,10 +88,10 @@ static int r600_draw_common(struct r600_draw *draw)
 	r = r600_pipe_shader_update(draw->ctx, rctx->ps_shader);
 	if (r)
 		return r;
-	r = radeon_draw_set(&rctx->draw, &rctx->vs_shader->rstate);
+	r = radeon_draw_set(rctx->draw, rctx->vs_shader->rstate);
 	if (r)
 		return r;
-	r = radeon_draw_set(&rctx->draw, &rctx->ps_shader->rstate);
+	r = radeon_draw_set(rctx->draw, rctx->ps_shader->rstate);
 	if (r)
 		return r;
 
@@ -101,68 +101,68 @@ static int r600_draw_common(struct r600_draw *draw)
 		rbuffer = (struct r600_resource*)vertex_buffer->buffer;
 		offset = rctx->vertex_elements->elements[i].src_offset + vertex_buffer->buffer_offset;
 		format = r600_translate_colorformat(rctx->vertex_elements->elements[i].src_format);
-		r = radeon_state_init(&vs_resource, rscreen->rw, R600_VS_RESOURCE_TYPE, R600_VS_RESOURCE + i);
-		if (r)
-			return r;
-		vs_resource.bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
-		vs_resource.nbo = 1;
-		vs_resource.states[R600_PS_RESOURCE__RESOURCE0_WORD0] = offset;
-		vs_resource.states[R600_PS_RESOURCE__RESOURCE0_WORD1] = rbuffer->bo->size - offset;
-		vs_resource.states[R600_PS_RESOURCE__RESOURCE0_WORD2] = S_038008_STRIDE(vertex_buffer->stride) |
+		vs_resource = radeon_state(rscreen->rw, R600_VS_RESOURCE_TYPE, R600_VS_RESOURCE + i);
+		if (vs_resource == NULL)
+			return -ENOMEM;
+		vs_resource->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+		vs_resource->nbo = 1;
+		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD0] = offset;
+		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD1] = rbuffer->bo->size - offset;
+		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = S_038008_STRIDE(vertex_buffer->stride) |
 								S_038008_DATA_FORMAT(format);
-		vs_resource.states[R600_PS_RESOURCE__RESOURCE0_WORD3] = 0x00000000;
-		vs_resource.states[R600_PS_RESOURCE__RESOURCE0_WORD4] = 0x00000000;
-		vs_resource.states[R600_PS_RESOURCE__RESOURCE0_WORD5] = 0x00000000;
-		vs_resource.states[R600_PS_RESOURCE__RESOURCE0_WORD6] = 0xC0000000;
-		vs_resource.placement[0] = RADEON_GEM_DOMAIN_GTT;
-		vs_resource.placement[1] = RADEON_GEM_DOMAIN_GTT;
-		radeon_state_pm4(&vs_resource);
-		r = radeon_draw_set(&rctx->draw, &vs_resource);
+		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = 0x00000000;
+		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD4] = 0x00000000;
+		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD5] = 0x00000000;
+		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD6] = 0xC0000000;
+		vs_resource->placement[0] = RADEON_GEM_DOMAIN_GTT;
+		vs_resource->placement[1] = RADEON_GEM_DOMAIN_GTT;
+		r = radeon_draw_set_new(rctx->draw, vs_resource);
 		if (r)
 			return r;
 	}
 	/* FIXME start need to change winsys */
-	r = radeon_state_init(&draw->draw, rscreen->rw, R600_DRAW_TYPE, R600_DRAW);
-	if (r)
-		return r;
-	draw->draw.states[R600_DRAW__VGT_NUM_INDICES] = draw->count;
-	draw->draw.states[R600_DRAW__VGT_DRAW_INITIATOR] = vgt_draw_initiator;
+	draw->draw = radeon_state(rscreen->rw, R600_DRAW_TYPE, R600_DRAW);
+	if (draw->draw == NULL)
+		return -ENOMEM;
+	draw->draw->states[R600_DRAW__VGT_NUM_INDICES] = draw->count;
+	draw->draw->states[R600_DRAW__VGT_DRAW_INITIATOR] = vgt_draw_initiator;
 	if (draw->index_buffer) {
-		rbuffer = (struct r600_resource*)draw->index_buffer;
-		draw->draw.bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
-		draw->draw.placement[0] = RADEON_GEM_DOMAIN_GTT;
-		draw->draw.placement[1] = RADEON_GEM_DOMAIN_GTT;
-		draw->draw.nbo = 1;
+		rbuffer = (struct r600_buffer*)draw->index_buffer;
+		draw->draw->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+		draw->draw->placement[0] = RADEON_GEM_DOMAIN_GTT;
+		draw->draw->placement[1] = RADEON_GEM_DOMAIN_GTT;
+		draw->draw->nbo = 1;
 	}
-	radeon_state_pm4(&draw->draw);
-	r = radeon_draw_set(&rctx->draw, &draw->draw);
+	r = radeon_draw_set_new(rctx->draw, draw->draw);
 	if (r)
 		return r;
-	r = radeon_state_init(&draw->vgt, rscreen->rw, R600_VGT_TYPE, R600_VGT);
-	if (r)
-		return r;
-	draw->vgt.states[R600_VGT__VGT_PRIMITIVE_TYPE] = prim;
-	draw->vgt.states[R600_VGT__VGT_MAX_VTX_INDX] = 0x00FFFFFF;
-	draw->vgt.states[R600_VGT__VGT_MIN_VTX_INDX] = 0x00000000;
-	draw->vgt.states[R600_VGT__VGT_INDX_OFFSET] = draw->start;
-	draw->vgt.states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX] = 0x00000000;
-	draw->vgt.states[R600_VGT__VGT_DMA_INDEX_TYPE] = vgt_dma_index_type;
-	draw->vgt.states[R600_VGT__VGT_PRIMITIVEID_EN] = 0x00000000;
-	draw->vgt.states[R600_VGT__VGT_DMA_NUM_INSTANCES] = 0x00000001;
-	draw->vgt.states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_EN] = 0x00000000;
-	draw->vgt.states[R600_VGT__VGT_INSTANCE_STEP_RATE_0] = 0x00000000;
-	draw->vgt.states[R600_VGT__VGT_INSTANCE_STEP_RATE_1] = 0x00000000;
-	radeon_state_pm4(&draw->vgt);
-	r = radeon_draw_set(&rctx->draw, &draw->vgt);
+	draw->vgt = radeon_state(rscreen->rw, R600_VGT_TYPE, R600_VGT);
+	if (draw->vgt == NULL)
+		return -ENOMEM;
+	draw->vgt->states[R600_VGT__VGT_PRIMITIVE_TYPE] = prim;
+	draw->vgt->states[R600_VGT__VGT_MAX_VTX_INDX] = 0x00FFFFFF;
+	draw->vgt->states[R600_VGT__VGT_MIN_VTX_INDX] = 0x00000000;
+	draw->vgt->states[R600_VGT__VGT_INDX_OFFSET] = draw->start;
+	draw->vgt->states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX] = 0x00000000;
+	draw->vgt->states[R600_VGT__VGT_DMA_INDEX_TYPE] = vgt_dma_index_type;
+	draw->vgt->states[R600_VGT__VGT_PRIMITIVEID_EN] = 0x00000000;
+	draw->vgt->states[R600_VGT__VGT_DMA_NUM_INSTANCES] = 0x00000001;
+	draw->vgt->states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_EN] = 0x00000000;
+	draw->vgt->states[R600_VGT__VGT_INSTANCE_STEP_RATE_0] = 0x00000000;
+	draw->vgt->states[R600_VGT__VGT_INSTANCE_STEP_RATE_1] = 0x00000000;
+	r = radeon_draw_set_new(rctx->draw, draw->vgt);
 	if (r)
 		return r;
 	/* FIXME */
-	r = radeon_ctx_set_draw(&rctx->ctx, &rctx->draw);
+	r = radeon_ctx_set_draw_new(rctx->ctx, rctx->draw);
 	if (r == -EBUSY) {
 		r600_flush(draw->ctx, 0, NULL);
-		r = radeon_ctx_set_draw(&rctx->ctx, &rctx->draw);
+		r = radeon_ctx_set_draw_new(rctx->ctx, rctx->draw);
 	}
-	return r;
+	if (r)
+		return r;
+	rctx->draw = radeon_draw_duplicate(rctx->draw);
+	return 0;
 }
 
 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)