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authorAndreas Hartmetz <[email protected]>2013-12-07 02:08:27 +0100
committerMarek Olšák <[email protected]>2013-12-12 18:34:11 +0100
commitca5812b45c09aabe2f2c400c323b4f2cc23ca93c (patch)
treebf829542cd458deee523ab7931132aa2fed05aa3 /src/gallium/drivers/r600/r600_blit.c
parent91aca8c662faf0ec311968b2897a72a6d08b199d (diff)
radeon: rearrange r600_texture and related code a bit.
This should make the differences and similarities between color and depth buffer handling more clear.
Diffstat (limited to 'src/gallium/drivers/r600/r600_blit.c')
-rw-r--r--src/gallium/drivers/r600/r600_blit.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c
index d3e9ec9c9d4..b80360cd86b 100644
--- a/src/gallium/drivers/r600/r600_blit.c
+++ b/src/gallium/drivers/r600/r600_blit.c
@@ -547,9 +547,9 @@ static void r600_clear(struct pipe_context *ctx, unsigned buffers,
* disable fast clear for texture array.
*/
/* Only use htile for first level */
- if (rtex->htile && !level && rtex->surface.array_size == 1) {
- if (rtex->depth_clear != depth) {
- rtex->depth_clear = depth;
+ if (rtex->htile_buffer && !level && rtex->surface.array_size == 1) {
+ if (rtex->depth_clear_value != depth) {
+ rtex->depth_clear_value = depth;
rctx->db_state.atom.dirty = true;
}
rctx->db_misc_state.htile_clear = true;