diff options
| author | Dave Airlie <[email protected]> | 2012-01-18 15:16:55 +0000 |
|---|---|---|
| committer | Dave Airlie <[email protected]> | 2012-01-20 17:58:53 +0000 |
| commit | c96b9834032952492efbd2d1f5511fe225704918 (patch) | |
| tree | 783d9d5e44adff586afbd3079c916f0d0a7a0db9 /src/gallium/drivers/r600/r600_asm.h | |
| parent | 0e019cbd1ca4ad8a11c9310d701ca4aab11b5951 (diff) | |
r600g: fixup AR handling (v5)
So it appears R600s (except rv670) do AR handling different using a different
opcode. This patch fixes up r600g to work properly on r600.
This fixes ~100 piglit tests here (in GLSL1.30 mode) on rv610.
v3: add index_mode as per the docs.
This still fails any dst relative tests for some reason I can't quite see yet,
but it passes a lot more tests than without.
v4: add a nop after dst.rel this could be improved using a second pass,
where we only insert nops if two instructions are sure to collide.
The docs say r600, rv610, rv630 needs this, and not rv670, rs780, rs880,
need AMD to confirm rv620, rv635.
v5: add is_nop_inst.
NOTE: This is a candidate for stable branches.
Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/gallium/drivers/r600/r600_asm.h')
| -rw-r--r-- | src/gallium/drivers/r600/r600_asm.h | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/src/gallium/drivers/r600/r600_asm.h b/src/gallium/drivers/r600/r600_asm.h index d0ff75d6e2f..00f7e591ac3 100644 --- a/src/gallium/drivers/r600/r600_asm.h +++ b/src/gallium/drivers/r600/r600_asm.h @@ -54,6 +54,7 @@ struct r600_bytecode_alu { unsigned bank_swizzle; unsigned bank_swizzle_force; unsigned omod; + unsigned index_mode; }; struct r600_bytecode_tex { @@ -176,6 +177,10 @@ struct r600_cf_callstack { int max; }; +#define AR_HANDLE_NORMAL 0 +#define AR_HANDLE_RV6XX 1 /* except RV670 */ + + struct r600_bytecode { enum chip_class chip_class; int type; @@ -194,13 +199,15 @@ struct r600_bytecode { struct r600_cf_callstack callstack[SQ_MAX_CALL_DEPTH]; unsigned ar_loaded; unsigned ar_reg; + unsigned ar_handling; + unsigned r6xx_nop_after_rel_dst; }; /* eg_asm.c */ int eg_bytecode_cf_build(struct r600_bytecode *bc, struct r600_bytecode_cf *cf); /* r600_asm.c */ -void r600_bytecode_init(struct r600_bytecode *bc, enum chip_class chip_class); +void r600_bytecode_init(struct r600_bytecode *bc, enum chip_class chip_class, enum radeon_family family); void r600_bytecode_clear(struct r600_bytecode *bc); int r600_bytecode_add_alu(struct r600_bytecode *bc, const struct r600_bytecode_alu *alu); int r600_bytecode_add_vtx(struct r600_bytecode *bc, const struct r600_bytecode_vtx *vtx); |