diff options
| author | Vadim Girlin <[email protected]> | 2012-01-15 18:56:36 +0400 |
|---|---|---|
| committer | Dave Airlie <[email protected]> | 2012-01-15 16:04:59 +0000 |
| commit | d84ab821c5f5bfe9f6a57e434af9ca06d54f45b3 (patch) | |
| tree | 77400de37a10511a07f20769349644b29b4752c3 /src/gallium/drivers/r600/r600_asm.c | |
| parent | 332e1d6d84353b8fac0b9619488b9dc83fe9ace1 (diff) | |
r600g: add support for ISHR/USHR/SHL on r600-evergreen
Signed-off-by: Vadim Girlin <[email protected]>
Diffstat (limited to 'src/gallium/drivers/r600/r600_asm.c')
| -rw-r--r-- | src/gallium/drivers/r600/r600_asm.c | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/src/gallium/drivers/r600/r600_asm.c b/src/gallium/drivers/r600/r600_asm.c index 3b281c60e39..23350e25967 100644 --- a/src/gallium/drivers/r600/r600_asm.c +++ b/src/gallium/drivers/r600/r600_asm.c @@ -86,6 +86,9 @@ static inline unsigned int r600_bytecode_get_num_operands(struct r600_bytecode * case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE: case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE: case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT: + case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT: + case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT: + case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT: return 2; case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV: @@ -161,6 +164,9 @@ static inline unsigned int r600_bytecode_get_num_operands(struct r600_bytecode * case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY: case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW: case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT: + case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT: + case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT: + case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT: return 2; case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV: @@ -505,10 +511,7 @@ static int is_alu_trans_unit_inst(struct r600_bytecode *bc, struct r600_bytecode /* Note that FLT_TO_INT_* instructions are vector-only instructions * on Evergreen, despite what the documentation says. FLT_TO_INT * can do both vector and scalar. */ - return alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT || - alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT || - alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT || - alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT || + return alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT || alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT || alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT || alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT || |