r600g: rework state emission of constant buffers

Framerate in ipers:
  before: 43.6 FPS
  after:  46.6 FPS

Reviewed-by: Alex Deucher <[email protected]>

1 files changed, 71 insertions, 0 deletions

diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 00d2d0d6163..e97f8e3a3b4 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1763,11 +1763,82 @@ static void evergreen_emit_vertex_buffers(struct r600_context *rctx, struct r600
 	}
 }
 
+static void evergreen_emit_constant_buffer(struct r600_context *rctx,
+					   struct r600_constbuf_state *state,
+				           unsigned buffer_id_base,
+				           unsigned reg_alu_constbuf_size,
+				           unsigned reg_alu_const_cache)
+{
+	struct radeon_winsys_cs *cs = rctx->cs;
+	uint32_t dirty_mask = state->dirty_mask;
+
+	while (dirty_mask) {
+		struct r600_constant_buffer *cb;
+		struct r600_resource *rbuffer;
+		uint64_t va;
+		unsigned buffer_index = ffs(dirty_mask) - 1;
+
+		cb = &state->cb[buffer_index];
+		rbuffer = (struct r600_resource*)cb->buffer;
+		assert(rbuffer);
+
+		va = r600_resource_va(&rctx->screen->screen, &rbuffer->b.b.b);
+		va += cb->buffer_offset;
+
+		r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
+				       ALIGN_DIVUP(cb->buffer_size >> 4, 16));
+		r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, va >> 8);
+
+		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
+		r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
+
+		r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
+		r600_write_value(cs, (buffer_id_base + buffer_index) * 8);
+		r600_write_value(cs, va); /* RESOURCEi_WORD0 */
+		r600_write_value(cs, rbuffer->buf->size - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
+		r600_write_value(cs, /* RESOURCEi_WORD2 */
+				 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
+				 S_030008_STRIDE(16) |
+				 S_030008_BASE_ADDRESS_HI(va >> 32UL));
+		r600_write_value(cs, /* RESOURCEi_WORD3 */
+				 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
+				 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
+				 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
+				 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
+		r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
+		r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
+		r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
+		r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
+
+		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
+		r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
+
+		dirty_mask &= ~(1 << buffer_index);
+	}
+	state->dirty_mask = 0;
+}
+
+static void evergreen_emit_vs_constant_buffer(struct r600_context *rctx, struct r600_atom *atom)
+{
+	evergreen_emit_constant_buffer(rctx, &rctx->vs_constbuf_state, 176,
+				       R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
+				       R_028980_ALU_CONST_CACHE_VS_0);
+}
+
+static void evergreen_emit_ps_constant_buffer(struct r600_context *rctx, struct r600_atom *atom)
+{
+	evergreen_emit_constant_buffer(rctx, &rctx->ps_constbuf_state, 0,
+				       R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
+				       R_028940_ALU_CONST_CACHE_PS_0);
+}
+
 void evergreen_init_state_functions(struct r600_context *rctx)
 {
 	r600_init_atom(&rctx->db_misc_state.atom, evergreen_emit_db_misc_state, 6, 0);
 	r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
 	r600_init_atom(&rctx->vertex_buffer_state, evergreen_emit_vertex_buffers, 0, 0);
+	r600_init_atom(&rctx->vs_constbuf_state.atom, evergreen_emit_vs_constant_buffer, 0, 0);
+	r600_init_atom(&rctx->ps_constbuf_state.atom, evergreen_emit_ps_constant_buffer, 0, 0);
 
 	rctx->context.create_blend_state = evergreen_create_blend_state;
 	rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;