diff options
| author | Andreas Hartmetz <[email protected]> | 2013-12-07 02:08:27 +0100 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2013-12-12 18:34:11 +0100 |
| commit | ca5812b45c09aabe2f2c400c323b4f2cc23ca93c (patch) | |
| tree | bf829542cd458deee523ab7931132aa2fed05aa3 /src/gallium/drivers/r600/evergreen_state.c | |
| parent | 91aca8c662faf0ec311968b2897a72a6d08b199d (diff) | |
radeon: rearrange r600_texture and related code a bit.
This should make the differences and similarities between color and
depth buffer handling more clear.
Diffstat (limited to 'src/gallium/drivers/r600/evergreen_state.c')
| -rw-r--r-- | src/gallium/drivers/r600/evergreen_state.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index 6faa53865fe..d5c1792cfb6 100644 --- a/src/gallium/drivers/r600/evergreen_state.c +++ b/src/gallium/drivers/r600/evergreen_state.c @@ -1696,8 +1696,8 @@ static void evergreen_init_depth_surface(struct r600_context *rctx, surf->htile_enabled = 0; /* use htile only for first level */ - if (rtex->htile && !level) { - uint64_t va = r600_resource_va(&rctx->screen->b.b, &rtex->htile->b.b); + if (rtex->htile_buffer && !level) { + uint64_t va = r600_resource_va(&rctx->screen->b.b, &rtex->htile_buffer->b.b); surf->htile_enabled = 1; surf->db_htile_data_base = va >> 8; surf->db_htile_surface = S_028ABC_HTILE_WIDTH(1) | @@ -1732,7 +1732,7 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx, rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB; rtex = (struct r600_texture*)rctx->framebuffer.state.zsbuf->texture; - if (rtex->htile) { + if (rtex->htile_buffer) { rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB_META; } } @@ -2362,11 +2362,11 @@ static void evergreen_emit_db_state(struct r600_context *rctx, struct r600_atom struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture; unsigned reloc_idx; - r600_write_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear)); + r600_write_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value)); r600_write_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, a->rsurf->db_htile_surface); r600_write_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, a->rsurf->db_preload_control); r600_write_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base); - reloc_idx = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rtex->htile, RADEON_USAGE_READWRITE); + reloc_idx = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rtex->htile_buffer, RADEON_USAGE_READWRITE); cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); cs->buf[cs->cdw++] = reloc_idx; } else { |