diff options
| author | Marek Olšák <[email protected]> | 2012-08-02 01:43:01 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2012-08-04 14:05:52 +0200 |
| commit | cb922b63eba1d75706354614bc5de4d39dbe9ad3 (patch) | |
| tree | a3d2a0c46db235c4546d5a3d8cefdbf75a5859a6 /src/gallium/drivers/r600/evergreen_compute_internal.c | |
| parent | cdc681c3ad746fe8adab4ea71358bcc54e024ff9 (diff) | |
r600g: precompute color buffer state in pipe_surface and reuse it
Diffstat (limited to 'src/gallium/drivers/r600/evergreen_compute_internal.c')
| -rw-r--r-- | src/gallium/drivers/r600/evergreen_compute_internal.c | 22 |
1 files changed, 21 insertions, 1 deletions
diff --git a/src/gallium/drivers/r600/evergreen_compute_internal.c b/src/gallium/drivers/r600/evergreen_compute_internal.c index fe224351855..6994432c88c 100644 --- a/src/gallium/drivers/r600/evergreen_compute_internal.c +++ b/src/gallium/drivers/r600/evergreen_compute_internal.c @@ -266,6 +266,9 @@ void evergreen_set_rat( struct r600_pipe_state * state = CALLOC_STRUCT(r600_pipe_state); struct pipe_surface rat_templ; + struct r600_surface *surf; + struct r600_resource *res; + struct r600_context *rctx = pipe->ctx; COMPUTE_DBG("bind rat: %i \n", id); @@ -291,9 +294,26 @@ void evergreen_set_rat( * of this driver. */ pipe->ctx->compute_cb_target_mask |= (0xf << (id * 4)); + surf = (struct r600_surface*)pipe->ctx->framebuffer.cbufs[id]; + res = (struct r600_resource*)surf->base.texture; + + evergreen_init_color_surface(rctx, surf); /* Get the CB register writes for the RAT */ - evergreen_cb(pipe->ctx, state, &pipe->ctx->framebuffer, id); + r600_pipe_state_add_reg_bo(state, R_028C60_CB_COLOR0_BASE + id * 0x3C, + surf->cb_color_base, res, RADEON_USAGE_READWRITE); + r600_pipe_state_add_reg(state, R_028C78_CB_COLOR0_DIM + id * 0x3C, + surf->cb_color_dim); + r600_pipe_state_add_reg_bo(state, R_028C70_CB_COLOR0_INFO + id * 0x3C, + surf->cb_color_info, res, RADEON_USAGE_READWRITE); + r600_pipe_state_add_reg(state, R_028C64_CB_COLOR0_PITCH + id * 0x3C, + surf->cb_color_pitch); + r600_pipe_state_add_reg(state, R_028C68_CB_COLOR0_SLICE + id * 0x3C, + surf->cb_color_slice); + r600_pipe_state_add_reg(state, R_028C6C_CB_COLOR0_VIEW + id * 0x3C, + surf->cb_color_view); + r600_pipe_state_add_reg_bo(state, R_028C74_CB_COLOR0_ATTRIB + id * 0x3C, + surf->cb_color_attrib, res, RADEON_USAGE_READWRITE); /* Add the register blocks to the dirty list */ free(pipe->ctx->states[R600_PIPE_STATE_FRAMEBUFFER]); |