r600g: atomize framebuffer state

Tested on RS880, Evergreen and Cayman.

Reviewed-by: Alex Deucher <[email protected]>

1 files changed, 4 insertions, 27 deletions

diff --git a/src/gallium/drivers/r600/evergreen_compute_internal.c b/src/gallium/drivers/r600/evergreen_compute_internal.c
index dc957320685..d4e9ed6eb05 100644
--- a/src/gallium/drivers/r600/evergreen_compute_internal.c
+++ b/src/gallium/drivers/r600/evergreen_compute_internal.c
@@ -264,10 +264,8 @@ void evergreen_set_rat(
 	assert((size & 3) == 0);
 	assert((start & 0xFF) == 0);
 
-	struct r600_pipe_state * state = CALLOC_STRUCT(r600_pipe_state);
 	struct pipe_surface rat_templ;
 	struct r600_surface *surf;
-	struct r600_resource *res;
 	struct r600_context *rctx = pipe->ctx;
 
 	COMPUTE_DBG("bind rat: %i \n", id);
@@ -281,12 +279,13 @@ void evergreen_set_rat(
 	rat_templ.u.tex.last_layer = 0;
 
 	/* Add the RAT the list of color buffers */
-	pipe->ctx->framebuffer.cbufs[id] = pipe->ctx->context.create_surface(
+	pipe->ctx->framebuffer.state.cbufs[id] = pipe->ctx->context.create_surface(
 		(struct pipe_context *)pipe->ctx,
 		(struct pipe_resource *)bo, &rat_templ);
 
 	/* Update the number of color buffers */
-	pipe->ctx->nr_cbufs = MAX2(id + 1, pipe->ctx->nr_cbufs);
+	pipe->ctx->framebuffer.state.nr_cbufs =
+		MAX2(id + 1, pipe->ctx->framebuffer.state.nr_cbufs);
 
 	/* Update the cb_target_mask
 	 * XXX: I think this is a potential spot for bugs once we start doing
@@ -294,31 +293,9 @@ void evergreen_set_rat(
 	 * of this driver. */
 	pipe->ctx->compute_cb_target_mask |= (0xf << (id * 4));
 
-	surf = (struct r600_surface*)pipe->ctx->framebuffer.cbufs[id];
-	res = (struct r600_resource*)surf->base.texture;
+	surf = (struct r600_surface*)pipe->ctx->framebuffer.state.cbufs[id];
 
 	evergreen_init_color_surface(rctx, surf);
-
-	/* Get the CB register writes for the RAT */
-	r600_pipe_state_add_reg_bo(state, R_028C60_CB_COLOR0_BASE + id * 0x3C,
-				   surf->cb_color_base, res, RADEON_USAGE_READWRITE);
-	r600_pipe_state_add_reg(state, R_028C78_CB_COLOR0_DIM + id * 0x3C,
-				surf->cb_color_dim);
-	r600_pipe_state_add_reg_bo(state, R_028C70_CB_COLOR0_INFO + id * 0x3C,
-				   surf->cb_color_info, res, RADEON_USAGE_READWRITE);
-	r600_pipe_state_add_reg(state, R_028C64_CB_COLOR0_PITCH + id * 0x3C,
-				surf->cb_color_pitch);
-	r600_pipe_state_add_reg(state, R_028C68_CB_COLOR0_SLICE + id * 0x3C,
-				surf->cb_color_slice);
-	r600_pipe_state_add_reg(state, R_028C6C_CB_COLOR0_VIEW + id * 0x3C,
-				surf->cb_color_view);
-	r600_pipe_state_add_reg_bo(state, R_028C74_CB_COLOR0_ATTRIB + id * 0x3C,
-				   surf->cb_color_attrib, res, RADEON_USAGE_READWRITE);
-
-	/* Add the register blocks to the dirty list */
-        free(pipe->ctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
-        pipe->ctx->states[R600_PIPE_STATE_FRAMEBUFFER] = state;
-        r600_context_pipe_state_set(pipe->ctx, state);
 }
 
 void evergreen_set_gds(