diff options
author | Alex Deucher <[email protected]> | 2012-10-23 11:30:31 -0400 |
---|---|---|
committer | Alex Deucher <[email protected]> | 2012-10-26 09:32:33 -0400 |
commit | 480e1463057c70ca1b197cbba5a9b1c153d8b052 (patch) | |
tree | 3b84c4f5e0dd084a0abea6c8d07c312b496d996e /src/gallium/drivers/r600/evergreen_compute.c | |
parent | 4a9341498582891761e91599729adf6f2e2728a8 (diff) |
r600g/compute: always CONTEXT_CONTROL packet at start of CS
It's required. The CP uses this to properly allocate new
contexts. Also do a CS partial flush since we are updating
CONFIG regs which are single state.
Signed-off-by: Alex Deucher <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
Reviewed-by: Tom Stellard <[email protected]>
Diffstat (limited to 'src/gallium/drivers/r600/evergreen_compute.c')
-rw-r--r-- | src/gallium/drivers/r600/evergreen_compute.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/gallium/drivers/r600/evergreen_compute.c b/src/gallium/drivers/r600/evergreen_compute.c index 25263f3b013..ce17d3a61ec 100644 --- a/src/gallium/drivers/r600/evergreen_compute.c +++ b/src/gallium/drivers/r600/evergreen_compute.c @@ -626,6 +626,15 @@ void evergreen_init_atom_start_compute_cs(struct r600_context *ctx) r600_init_command_buffer(cb, 256); cb->pkt_flags = RADEON_CP_PACKET3_COMPUTE_MODE; + /* This must be first. */ + r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0)); + r600_store_value(cb, 0x80000000); + r600_store_value(cb, 0x80000000); + + /* We're setting config registers here. */ + r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0)); + r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_CS_PARTIAL_FLUSH) | EVENT_INDEX(4)); + switch (ctx->family) { case CHIP_CEDAR: default: |