diff options
author | Glenn Kennard <[email protected]> | 2014-10-15 17:12:16 +0200 |
---|---|---|
committer | Marek Olšák <[email protected]> | 2014-10-28 23:20:45 +0100 |
commit | 7b1c0cbc90d456384b0950ad21faa3c61a6b43ff (patch) | |
tree | 13e81fc5dcfcf58f68accc686e907588ec29275f /src/gallium/drivers/r600/eg_asm.c | |
parent | 444c8c2f287d6553b7d9c5cdf721dcb7624e01a9 (diff) |
r600g: Implement sm5 UBO/sampler indexing
Caveat: Shaders using UBO/sampler indexing will
not be optimized by SB, due to SB not currently
supporting the necessary CF_INDEX_[01] index
registers.
Signed-off-by: Glenn Kennard <[email protected]>
Diffstat (limited to 'src/gallium/drivers/r600/eg_asm.c')
-rw-r--r-- | src/gallium/drivers/r600/eg_asm.c | 52 |
1 files changed, 48 insertions, 4 deletions
diff --git a/src/gallium/drivers/r600/eg_asm.c b/src/gallium/drivers/r600/eg_asm.c index acb30409428..295cb4d80b7 100644 --- a/src/gallium/drivers/r600/eg_asm.c +++ b/src/gallium/drivers/r600/eg_asm.c @@ -43,10 +43,10 @@ int eg_bytecode_cf_build(struct r600_bytecode *bc, struct r600_bytecode_cf *cf) /* prepend ALU_EXTENDED if we need more than 2 kcache sets */ if (cf->eg_alu_extended) { bc->bytecode[id++] = - S_SQ_CF_ALU_WORD0_EXT_KCACHE_BANK_INDEX_MODE0(V_SQ_CF_INDEX_NONE) | - S_SQ_CF_ALU_WORD0_EXT_KCACHE_BANK_INDEX_MODE1(V_SQ_CF_INDEX_NONE) | - S_SQ_CF_ALU_WORD0_EXT_KCACHE_BANK_INDEX_MODE2(V_SQ_CF_INDEX_NONE) | - S_SQ_CF_ALU_WORD0_EXT_KCACHE_BANK_INDEX_MODE3(V_SQ_CF_INDEX_NONE) | + S_SQ_CF_ALU_WORD0_EXT_KCACHE_BANK_INDEX_MODE0(cf->kcache[0].index_mode) | + S_SQ_CF_ALU_WORD0_EXT_KCACHE_BANK_INDEX_MODE1(cf->kcache[1].index_mode) | + S_SQ_CF_ALU_WORD0_EXT_KCACHE_BANK_INDEX_MODE2(cf->kcache[2].index_mode) | + S_SQ_CF_ALU_WORD0_EXT_KCACHE_BANK_INDEX_MODE3(cf->kcache[3].index_mode) | S_SQ_CF_ALU_WORD0_EXT_KCACHE_BANK2(cf->kcache[2].bank) | S_SQ_CF_ALU_WORD0_EXT_KCACHE_BANK3(cf->kcache[3].bank) | S_SQ_CF_ALU_WORD0_EXT_KCACHE_MODE2(cf->kcache[2].mode); @@ -143,3 +143,47 @@ void eg_bytecode_export_read(struct r600_bytecode *bc, output->comp_mask = G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(word1); } #endif + +int egcm_load_index_reg(struct r600_bytecode *bc, unsigned id, bool inside_alu_clause) +{ + struct r600_bytecode_alu alu; + int r; + unsigned type; + + assert(id < 2); + assert(bc->chip_class >= EVERGREEN); + + if (bc->index_loaded[id]) + return 0; + + memset(&alu, 0, sizeof(alu)); + alu.op = ALU_OP1_MOVA_INT; + alu.src[0].sel = bc->index_reg[id]; + alu.src[0].chan = 0; + alu.last = 1; + r = r600_bytecode_add_alu(bc, &alu); + if (r) + return r; + + bc->ar_loaded = 0; /* clobbered */ + + memset(&alu, 0, sizeof(alu)); + alu.op = id == 0 ? ALU_OP0_SET_CF_IDX0 : ALU_OP0_SET_CF_IDX1; + alu.last = 1; + r = r600_bytecode_add_alu(bc, &alu); + if (r) + return r; + + /* Must split ALU group as index only applies to following group */ + if (inside_alu_clause) { + type = bc->cf_last->op; + if ((r = r600_bytecode_add_cf(bc))) { + return r; + } + bc->cf_last->op = type; + } + + bc->index_loaded[id] = 1; + + return 0; +} |