r600g: build fetch shader from vertex elements

Vertex elements change are less frequent than draw call, those to
avoid rebuilding fetch shader to often build the fetch shader along
vertex elements. This also allow to move vertex buffer setup out
of draw path and make update to it less frequent.

Shader update can still be improved to only update SPI regs (based
on some rasterizer state like flat shading or point sprite ...).

Signed-off-by: Jerome Glisse <[email protected]>

1 files changed, 35 insertions, 0 deletions

diff --git a/src/gallium/drivers/r600/eg_asm.c b/src/gallium/drivers/r600/eg_asm.c
index 21d66fa9564..b79875c7c75 100644
--- a/src/gallium/drivers/r600/eg_asm.c
+++ b/src/gallium/drivers/r600/eg_asm.c
@@ -27,6 +27,7 @@
 #include "r600_asm.h"
 #include "eg_sq.h"
 #include "r600_opcodes.h"
+#include "evergreend.h"
 
 int eg_bc_cf_build(struct r600_bc *bc, struct r600_bc_cf *cf)
 {
@@ -89,3 +90,37 @@ int eg_bc_cf_build(struct r600_bc *bc, struct r600_bc_cf *cf)
 	}
 	return 0;
 }
+
+void eg_cf_vtx(struct r600_vertex_element *ve, u32 *bytecode, unsigned count)
+{
+	struct r600_pipe_state *rstate;
+	unsigned i = 0;
+
+	if (count > 8) {
+		bytecode[i++] = S_SQ_CF_WORD0_ADDR(8 >> 1);
+		bytecode[i++] = S_SQ_CF_WORD1_CF_INST(EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX) |
+				S_SQ_CF_WORD1_BARRIER(1) |
+				S_SQ_CF_WORD1_COUNT(8 - 1);
+		bytecode[i++] = S_SQ_CF_WORD0_ADDR(40 >> 1);
+		bytecode[i++] = S_SQ_CF_WORD1_CF_INST(EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX) |
+				S_SQ_CF_WORD1_BARRIER(1) |
+				S_SQ_CF_WORD1_COUNT(count - 8 - 1);
+	} else {
+		bytecode[i++] = S_SQ_CF_WORD0_ADDR(8 >> 1);
+		bytecode[i++] = S_SQ_CF_WORD1_CF_INST(EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX) |
+				S_SQ_CF_WORD1_BARRIER(1) |
+				S_SQ_CF_WORD1_COUNT(count - 1);
+	}
+	bytecode[i++] = S_SQ_CF_WORD0_ADDR(0);
+	bytecode[i++] = S_SQ_CF_WORD1_CF_INST(EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN) |
+			S_SQ_CF_WORD1_BARRIER(1);
+
+	rstate = &ve->rstate;
+	rstate->id = R600_PIPE_STATE_FETCH_SHADER;
+	rstate->nregs = 0;
+	r600_pipe_state_add_reg(rstate, R_0288A8_SQ_PGM_RESOURCES_FS,
+				0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_START_FS,
+				(r600_bo_offset(ve->fetch_shader)) >> 8,
+				0xFFFFFFFF, ve->fetch_shader);
+}