r300: Unbreak emit, fix up a bunch of little things.

1 files changed, 37 insertions, 36 deletions

diff --git a/src/gallium/drivers/r300/r300_surface.c b/src/gallium/drivers/r300/r300_surface.c
index f2d0183c981..185b56ff88d 100644
--- a/src/gallium/drivers/r300/r300_surface.c
+++ b/src/gallium/drivers/r300/r300_surface.c
@@ -42,17 +42,10 @@ static void r300_surface_fill(struct pipe_context* pipe,
         " dimensions %dx%d, color 0x%x\n",
         dest, x, y, w, h, color);
 
-BEGIN_CS((caps->is_r500) ? 367 : 276);
+BEGIN_CS((caps->is_r500) ? 367 : 322);
 R300_PACIFY;
 OUT_CS_REG(R300_TX_INVALTAGS, 0x0);
 R300_PACIFY;
-/* Viewport setup */
-OUT_CS_REG(R300_SE_VPORT_XSCALE, 0x43000000);
-OUT_CS_REG(R300_SE_VPORT_XOFFSET, 0x43002000);
-OUT_CS_REG(R300_SE_VPORT_YSCALE, 0xC3000000);
-OUT_CS_REG(R300_SE_VPORT_YOFFSET, 0x43002000);
-OUT_CS_REG(R300_SE_VPORT_ZSCALE, 0x3F000000);
-OUT_CS_REG(R300_SE_VPORT_ZOFFSET, 0x3F000000);
 /* Flush PVS. */
 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
 
@@ -71,7 +64,7 @@ OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_0, 0x0);
 /* XXX magic number not in r300_reg */
 OUT_CS_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0xAAAAAAAA);
 OUT_CS_REG(R300_VAP_CLIP_CNTL, 0x0);
-OUT_CS_REG(R300_VAP_GB_VERT_CLIP_ADJ, 4);
+OUT_CS_REG_SEQ(R300_VAP_GB_VERT_CLIP_ADJ, 4);
 OUT_CS_32F(1.0);
 OUT_CS_32F(1.0);
 OUT_CS_32F(1.0);
@@ -149,9 +142,6 @@ OUT_CS_REG(R300_FG_DEPTH_SRC, 0x00000000);
 OUT_CS_REG(R300_RB3D_CCTL, 0x00000000);
 OUT_CS_REG(RB3D_COLOR_CHANNEL_MASK, 0x0000000F);
 
-r300_emit_blend_color_state(r300, &blend_color_clear_state);
-
-OUT_CS_REG(R300_RB3D_BLEND_COLOR, 0x00000000);
 /* XXX: Oh the wonderful unknown */
 OUT_CS_REG_SEQ(0x4E54, 8);
 for (i = 0; i < 8; i++)
@@ -184,16 +174,16 @@ OUT_CS_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0xAAAAAAAA);
 OUT_CS_REG(R300_VAP_OUTPUT_VTX_FMT_0, 0x00000003);
 OUT_CS_REG(R300_VAP_OUTPUT_VTX_FMT_1, 0x00000000);
 OUT_CS_REG(R300_TX_ENABLE, 0x0);
-OUT_CS_REG(R300_SE_VPORT_XSCALE, 0x3F800000);
-OUT_CS_REG(R300_SE_VPORT_XOFFSET, 0x00000000);
-OUT_CS_REG(R300_SE_VPORT_YSCALE, 0x3F800000);
-OUT_CS_REG(R300_SE_VPORT_YOFFSET, 0x00000000);
-OUT_CS_REG(R300_SE_VPORT_ZSCALE, 0x3F800000);
-OUT_CS_REG(R300_SE_VPORT_ZOFFSET, 0x00000000);
+/* XXX viewport setup */
+OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
+OUT_CS_32F(1.0);
+OUT_CS_32F(0.0);
+OUT_CS_32F(1.0);
+OUT_CS_32F(0.0);
+OUT_CS_32F(1.0);
+OUT_CS_32F(0.0);
 OUT_CS_REG(R300_FG_ALPHA_FUNC, 0x00000000);
 
-r300_emit_blend_state(r300, &blend_clear_state);
-
 OUT_CS_REG(R300_VAP_CLIP_CNTL, 0x0001C000);
 OUT_CS_REG(R300_GA_POINT_SIZE, ((h * 6) & R300_POINTSIZE_Y_MASK) |
     ((w * 6) << R300_POINTSIZE_X_SHIFT));
@@ -262,22 +252,22 @@ if (caps->is_r500) {
     for (i = 0; i < 8; i++) {
         OUT_CS(R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3));
     }
-}
-OUT_CS_REG(R300_RS_COUNT, (1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN);
-OUT_CS_REG(R300_RS_INST_COUNT, 0x0);
+    OUT_CS_REG(R300_RS_COUNT, (1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN);
+    OUT_CS_REG(R300_RS_INST_COUNT, 0x0);
 
-OUT_CS_REG(R300_RS_INST_0, 0x00004000);
-OUT_CS_REG(R300_US_CONFIG, 0x00000000);
-OUT_CS_REG(R300_US_PIXSIZE, 0x00000000);
-OUT_CS_REG(R300_US_CODE_OFFSET, 0x00000000);
-OUT_CS_REG(R300_US_CODE_ADDR_0, 0x00000000);
-OUT_CS_REG(R300_US_CODE_ADDR_1, 0x00000000);
-OUT_CS_REG(R300_US_CODE_ADDR_2, 0x00000000);
-OUT_CS_REG(R300_US_CODE_ADDR_3, 0x00400000);
-OUT_CS_REG(R300_US_ALU_RGB_INST_0, 0x00050A80);
-OUT_CS_REG(R300_US_ALU_RGB_ADDR_0, 0x1C000000);
-OUT_CS_REG(R300_US_ALU_ALPHA_INST_0, 0x00040889);
-OUT_CS_REG(R300_US_ALU_ALPHA_ADDR_0, 0x01000000);
+    OUT_CS_REG(R300_RS_INST_0, 0x00004000);
+    OUT_CS_REG(R300_US_CONFIG, 0x00000000);
+    OUT_CS_REG(R300_US_PIXSIZE, 0x00000000);
+    OUT_CS_REG(R300_US_CODE_OFFSET, 0x00000000);
+    OUT_CS_REG(R300_US_CODE_ADDR_0, 0x00000000);
+    OUT_CS_REG(R300_US_CODE_ADDR_1, 0x00000000);
+    OUT_CS_REG(R300_US_CODE_ADDR_2, 0x00000000);
+    OUT_CS_REG(R300_US_CODE_ADDR_3, 0x00400000);
+    OUT_CS_REG(R300_US_ALU_RGB_INST_0, 0x00050A80);
+    OUT_CS_REG(R300_US_ALU_RGB_ADDR_0, 0x1C000000);
+    OUT_CS_REG(R300_US_ALU_ALPHA_INST_0, 0x00040889);
+    OUT_CS_REG(R300_US_ALU_ALPHA_ADDR_0, 0x01000000);
+}
 /* XXX these magic numbers should be explained when
  * this becomes a cached state object */
 OUT_CS_REG(R300_VAP_CNTL, 0xA | (0x5 << R300_PVS_NUM_CNTLRS_SHIFT) |
@@ -300,12 +290,23 @@ OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0xD10021);
 OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0x1248021);
 OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0x0);
 
+r300_emit_blend_state(r300, &blend_clear_state);
+r300_emit_blend_color_state(r300, &blend_color_clear_state);
 r300_emit_dsa_state(r300, &dsa_clear_state);
 
 R300_PACIFY;
+/* Flush colorbuffer and blend caches. */
+OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT,
+    R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D |
+    R300_RB3D_DSTCACHE_CTLSTAT_DC_FINISH_SIGNAL);
+OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
+    R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
+    R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
+
 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0, 1);
 OUT_CS_RELOC(dest->buffer, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
-//OUT_CS_REG(R300_RB3D_COLORPITCH0, 0x00C00100);
+OUT_CS_REG(R300_RB3D_COLORPITCH0, (w >> 1) | R300_COLOR_TILE_ENABLE |
+    R300_COLOR_FORMAT_ARGB8888);
 OUT_CS_REG(RB3D_COLOR_CHANNEL_MASK, 0x0000000F);
 /* XXX Packet3 */
 OUT_CS(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8));