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authorMarek Olšák <[email protected]>2010-06-24 03:02:50 +0200
committerMarek Olšák <[email protected]>2010-06-24 06:10:47 +0200
commit6b15a8d2afa1cdf8577d48b1f1644358f1e47b47 (patch)
treec89f23375f67c2f1cd265a86630b75999861d092 /src/gallium/drivers/r300/r300_reg.h
parent7315300fa5a5e63c16b9e258feb4df76176b5b4b (diff)
r300g: add "has HiZ" flag, add ZMask regs
Diffstat (limited to 'src/gallium/drivers/r300/r300_reg.h')
-rw-r--r--src/gallium/drivers/r300/r300_reg.h18
1 files changed, 18 insertions, 0 deletions
diff --git a/src/gallium/drivers/r300/r300_reg.h b/src/gallium/drivers/r300/r300_reg.h
index c783998c78d..180560175a4 100644
--- a/src/gallium/drivers/r300/r300_reg.h
+++ b/src/gallium/drivers/r300/r300_reg.h
@@ -2673,6 +2673,24 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
/* Z Buffer Clear Value */
#define R300_ZB_DEPTHCLEARVALUE 0x4f28
+/* Z Mask RAM is a Z compression buffer.
+ * Each dword of the Z Mask contains compression info for 16 4x4 pixel blocks,
+ * that is 2 bits for each block.
+ * On chips with 2 Z pipes, every other dword maps to a different pipe.
+ */
+
+/* The dword offset into Z mask RAM (bits 18:4) */
+#define R300_ZB_ZMASK_OFFSET 0x4f30
+
+/* Z Mask Pitch. */
+#define R300_ZB_ZMASK_PITCH 0x4f34
+
+/* Access to Z Mask RAM in a manner similar to HiZ RAM.
+ * The indices are autoincrementing. */
+#define R300_ZB_ZMASK_WRINDEX 0x4f38
+#define R300_ZB_ZMASK_DWORD 0x4f3c
+#define R300_ZB_ZMASK_RDINDEX 0x4f40
+
/* Hierarchical Z Memory Offset */
#define R300_ZB_HIZ_OFFSET 0x4f44