diff options
| author | Marek Olšák <[email protected]> | 2013-08-11 02:15:12 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2013-08-27 23:18:54 +0200 |
| commit | adb93e3bda13ed539f383787c09f948d0f27fbcb (patch) | |
| tree | 146b838c9a9533cc8f0f1ef55778865afeffde00 /src/gallium/drivers/r300/r300_chipset.c | |
| parent | aa3905423e398e1ba36502ae91339d1303acf77f (diff) | |
r300g: enable MSAA on r300-r400, be careful about using color compression
MSAA was tested by one user on RS690 and it works for him with color
compression (CMASK) disabled. Our theory is that his chipset lacks CMASK RAM.
Since we don't have hardware documentation about which chipsets actually have
CMASK RAM, I had to take a guess based on the presence of HiZ.
Reviewed-by: Alex Deucher <[email protected]>
Diffstat (limited to 'src/gallium/drivers/r300/r300_chipset.c')
| -rw-r--r-- | src/gallium/drivers/r300/r300_chipset.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/gallium/drivers/r300/r300_chipset.c b/src/gallium/drivers/r300/r300_chipset.c index 30e085ac517..c1f5e3cee1f 100644 --- a/src/gallium/drivers/r300/r300_chipset.c +++ b/src/gallium/drivers/r300/r300_chipset.c @@ -84,6 +84,7 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) caps->num_vert_fpus = 0; caps->hiz_ram = 0; caps->zmask_ram = 0; + caps->has_cmask = FALSE; switch (caps->family) { @@ -91,6 +92,7 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) case CHIP_R350: caps->high_second_pipe = TRUE; caps->num_vert_fpus = 4; + caps->has_cmask = TRUE; /* guessed because there is also HiZ */ caps->hiz_ram = R300_HIZ_LIMIT; caps->zmask_ram = PIPE_ZMASK_SIZE; break; @@ -105,6 +107,7 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) case CHIP_RV380: caps->high_second_pipe = TRUE; caps->num_vert_fpus = 2; + caps->has_cmask = TRUE; /* guessed because there is also HiZ */ caps->hiz_ram = R300_HIZ_LIMIT; caps->zmask_ram = RV3xx_ZMASK_SIZE; break; @@ -127,24 +130,28 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) case CHIP_R481: case CHIP_RV410: caps->num_vert_fpus = 6; + caps->has_cmask = TRUE; /* guessed because there is also HiZ */ caps->hiz_ram = R300_HIZ_LIMIT; caps->zmask_ram = PIPE_ZMASK_SIZE; break; case CHIP_R520: caps->num_vert_fpus = 8; + caps->has_cmask = TRUE; caps->hiz_ram = R300_HIZ_LIMIT; caps->zmask_ram = PIPE_ZMASK_SIZE; break; case CHIP_RV515: caps->num_vert_fpus = 2; + caps->has_cmask = TRUE; caps->hiz_ram = R300_HIZ_LIMIT; caps->zmask_ram = PIPE_ZMASK_SIZE; break; case CHIP_RV530: caps->num_vert_fpus = 5; + caps->has_cmask = TRUE; caps->hiz_ram = RV530_HIZ_LIMIT; caps->zmask_ram = PIPE_ZMASK_SIZE; break; @@ -153,6 +160,7 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) case CHIP_RV560: case CHIP_RV570: caps->num_vert_fpus = 8; + caps->has_cmask = TRUE; caps->hiz_ram = RV530_HIZ_LIMIT; caps->zmask_ram = PIPE_ZMASK_SIZE; break; |