diff options
| author | Alyssa Rosenzweig <[email protected]> | 2019-07-15 15:34:50 -0700 |
|---|---|---|
| committer | Alyssa Rosenzweig <[email protected]> | 2019-07-16 07:19:28 -0700 |
| commit | e65e3cf596f1a3d0ac1e7bfdd28ebc3b72b4558e (patch) | |
| tree | da7b997f637e5f6632e1fa29cc14dcbb6909907f /src/gallium/drivers/panfrost/pan_resource.c | |
| parent | f7621a8c5f6f61f41196aa797c439cbee64d5233 (diff) | |
panfrost: AFBC buffers must be cache-line aligned
Fixes a DATA_INVALID_FAULT when AFBC is paried with mipmapping.
Signed-off-by: Alyssa Rosenzweig <[email protected]>
Diffstat (limited to 'src/gallium/drivers/panfrost/pan_resource.c')
| -rw-r--r-- | src/gallium/drivers/panfrost/pan_resource.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/gallium/drivers/panfrost/pan_resource.c b/src/gallium/drivers/panfrost/pan_resource.c index e630f1b579a..7b46acaf58b 100644 --- a/src/gallium/drivers/panfrost/pan_resource.c +++ b/src/gallium/drivers/panfrost/pan_resource.c @@ -287,6 +287,11 @@ panfrost_setup_slices(struct panfrost_resource *pres, size_t *bo_size) /* We don't need to align depth */ } + /* Align levels to cache-line as a performance improvement for + * linear/tiled and as a requirement for AFBC */ + + offset = ALIGN_POT(offset, 64); + slice->offset = offset; /* Compute the would-be stride */ |