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authorChristoph Bumiller <[email protected]>2013-04-06 17:40:02 +0200
committerChristoph Bumiller <[email protected]>2013-04-12 11:41:35 +0200
commit71c1c8a9b89ca1ecca1857c53cd8c648c9c9a871 (patch)
tree61af85b0911c1388e4107386bf4c21bff8eacd02 /src/gallium/drivers/nvc0
parent2b62ba7cb0e69cae721545e8775193f87955dec8 (diff)
nvc0: patch up TEX cases with 5 or 6 sources on nve4
Hackishly fixes alignment requirement of 2nd tuple for now.
Diffstat (limited to 'src/gallium/drivers/nvc0')
-rw-r--r--src/gallium/drivers/nvc0/codegen/nv50_ir_lowering_nvc0.cpp20
1 files changed, 19 insertions, 1 deletions
diff --git a/src/gallium/drivers/nvc0/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nvc0/codegen/nv50_ir_lowering_nvc0.cpp
index 5f0f2e72231..c459d60759b 100644
--- a/src/gallium/drivers/nvc0/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nvc0/codegen/nv50_ir_lowering_nvc0.cpp
@@ -728,13 +728,31 @@ NVC0LoweringPass::handleTEX(TexInstruction *i)
if (i->tex.useOffsets) {
uint32_t value = 0;
int n, c;
- int s = i->srcCount(0xff);
+ int s = i->srcCount(0xff, true);
+ if (i->srcExists(s)) // move potential predicate out of the way
+ i->moveSources(s, 1);
for (n = 0; n < i->tex.useOffsets; ++n)
for (c = 0; c < 3; ++c)
value |= (i->tex.offset[n][c] & 0xf) << (n * 12 + c * 4);
i->setSrc(s, bld.loadImm(NULL, value));
}
+ if (prog->getTarget()->getChipset() >= NVISA_GK104_CHIPSET) {
+ //
+ // If TEX requires more than 4 sources, the 2nd register tuple must be
+ // aligned to 4, even if it consists of just a single 4-byte register.
+ //
+ // XXX HACK: We insert 0 sources to avoid the 5 or 6 regs case.
+ //
+ int s = i->srcCount(0xff, true);
+ if (s > 4 && s < 7) {
+ if (i->srcExists(s)) // move potential predicate out of the way
+ i->moveSources(s, 7 - s);
+ while (s < 7)
+ i->setSrc(s++, bld.loadImm(NULL, 0));
+ }
+ }
+
return true;
}