nvc0: implement MP performance counters

There's more, but this only adds (most) of the counters that are
handled directly by the shader processors.
The other counter domains are not handled on the multiprocessor and
there are no FIFO object methods for configuring them.
Instead, they have to be programmed by the kernel via PCOUNTER, and
the interface for this isn't in place yet.

1 files changed, 70 insertions, 0 deletions

diff --git a/src/gallium/drivers/nvc0/nve4_compute.xml.h b/src/gallium/drivers/nvc0/nve4_compute.xml.h
index 2f110f57657..9a774668239 100644
--- a/src/gallium/drivers/nvc0/nve4_compute.xml.h
+++ b/src/gallium/drivers/nvc0/nve4_compute.xml.h
@@ -199,6 +199,76 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 #define NVE4_COMPUTE_UNK260c					0x0000260c
 
+#define NVE4_COMPUTE_MP_PM_SET(i0)			       (0x0000335c + 0x4*(i0))
+#define NVE4_COMPUTE_MP_PM_SET__ESIZE				0x00000004
+#define NVE4_COMPUTE_MP_PM_SET__LEN				0x00000008
+
+#define NVE4_COMPUTE_MP_PM_A_SIGSEL(i0)			       (0x0000337c + 0x4*(i0))
+#define NVE4_COMPUTE_MP_PM_A_SIGSEL__ESIZE			0x00000004
+#define NVE4_COMPUTE_MP_PM_A_SIGSEL__LEN			0x00000004
+#define NVE4_COMPUTE_MP_PM_A_SIGSEL_NONE			0x00000000
+#define NVE4_COMPUTE_MP_PM_A_SIGSEL_USER			0x00000001
+#define NVE4_COMPUTE_MP_PM_A_SIGSEL_LAUNCH			0x00000003
+#define NVE4_COMPUTE_MP_PM_A_SIGSEL_EXEC			0x00000004
+#define NVE4_COMPUTE_MP_PM_A_SIGSEL_ISSUE			0x00000005
+#define NVE4_COMPUTE_MP_PM_A_SIGSEL_LDST			0x0000001b
+#define NVE4_COMPUTE_MP_PM_A_SIGSEL_BRANCH			0x0000001c
+
+#define NVE4_COMPUTE_MP_PM_B_SIGSEL(i0)			       (0x0000338c + 0x4*(i0))
+#define NVE4_COMPUTE_MP_PM_B_SIGSEL__ESIZE			0x00000004
+#define NVE4_COMPUTE_MP_PM_B_SIGSEL__LEN			0x00000004
+#define NVE4_COMPUTE_MP_PM_B_SIGSEL_NONE			0x00000000
+#define NVE4_COMPUTE_MP_PM_B_SIGSEL_WARP			0x00000002
+#define NVE4_COMPUTE_MP_PM_B_SIGSEL_L1				0x00000010
+#define NVE4_COMPUTE_MP_PM_B_SIGSEL_MEM				0x00000011
+
+#define NVE4_COMPUTE_MP_PM_SRCSEL(i0)			       (0x0000339c + 0x4*(i0))
+#define NVE4_COMPUTE_MP_PM_SRCSEL__ESIZE			0x00000004
+#define NVE4_COMPUTE_MP_PM_SRCSEL__LEN				0x00000008
+#define NVE4_COMPUTE_MP_PM_SRCSEL_GRP0__MASK			0x00000003
+#define NVE4_COMPUTE_MP_PM_SRCSEL_GRP0__SHIFT			0
+#define NVE4_COMPUTE_MP_PM_SRCSEL_SIG0__MASK			0x0000001c
+#define NVE4_COMPUTE_MP_PM_SRCSEL_SIG0__SHIFT			2
+#define NVE4_COMPUTE_MP_PM_SRCSEL_GRP1__MASK			0x00000060
+#define NVE4_COMPUTE_MP_PM_SRCSEL_GRP1__SHIFT			5
+#define NVE4_COMPUTE_MP_PM_SRCSEL_SIG1__MASK			0x00000380
+#define NVE4_COMPUTE_MP_PM_SRCSEL_SIG1__SHIFT			7
+#define NVE4_COMPUTE_MP_PM_SRCSEL_GRP2__MASK			0x00000c00
+#define NVE4_COMPUTE_MP_PM_SRCSEL_GRP2__SHIFT			10
+#define NVE4_COMPUTE_MP_PM_SRCSEL_SIG2__MASK			0x00007000
+#define NVE4_COMPUTE_MP_PM_SRCSEL_SIG2__SHIFT			12
+#define NVE4_COMPUTE_MP_PM_SRCSEL_GRP3__MASK			0x00018000
+#define NVE4_COMPUTE_MP_PM_SRCSEL_GRP3__SHIFT			15
+#define NVE4_COMPUTE_MP_PM_SRCSEL_SIG3__MASK			0x000e0000
+#define NVE4_COMPUTE_MP_PM_SRCSEL_SIG3__SHIFT			17
+#define NVE4_COMPUTE_MP_PM_SRCSEL_GRP4__MASK			0x00300000
+#define NVE4_COMPUTE_MP_PM_SRCSEL_GRP4__SHIFT			20
+#define NVE4_COMPUTE_MP_PM_SRCSEL_SIG4__MASK			0x01c00000
+#define NVE4_COMPUTE_MP_PM_SRCSEL_SIG4__SHIFT			22
+#define NVE4_COMPUTE_MP_PM_SRCSEL_GRP5__MASK			0x06000000
+#define NVE4_COMPUTE_MP_PM_SRCSEL_GRP5__SHIFT			25
+#define NVE4_COMPUTE_MP_PM_SRCSEL_SIG5__MASK			0x38000000
+#define NVE4_COMPUTE_MP_PM_SRCSEL_SIG5__SHIFT			27
+
+#define NVE4_COMPUTE_MP_PM_FUNC(i0)			       (0x000033bc + 0x4*(i0))
+#define NVE4_COMPUTE_MP_PM_FUNC__ESIZE				0x00000004
+#define NVE4_COMPUTE_MP_PM_FUNC__LEN				0x00000008
+#define NVE4_COMPUTE_MP_PM_FUNC_MODE__MASK			0x0000000f
+#define NVE4_COMPUTE_MP_PM_FUNC_MODE__SHIFT			0
+#define NVE4_COMPUTE_MP_PM_FUNC_MODE_LOGOP			0x00000000
+#define NVE4_COMPUTE_MP_PM_FUNC_MODE_LOGOP_PULSE		0x00000001
+#define NVE4_COMPUTE_MP_PM_FUNC_MODE_B6				0x00000002
+#define NVE4_COMPUTE_MP_PM_FUNC_MODE_UNK3			0x00000003
+#define NVE4_COMPUTE_MP_PM_FUNC_MODE_LOGOP_B6			0x00000004
+#define NVE4_COMPUTE_MP_PM_FUNC_MODE_LOGOP_B6_PULSE		0x00000005
+#define NVE4_COMPUTE_MP_PM_FUNC_MODE_UNK6			0x00000006
+#define NVE4_COMPUTE_MP_PM_FUNC_MODE_UNK7			0x00000007
+#define NVE4_COMPUTE_MP_PM_FUNC_MODE_UNK8			0x00000008
+#define NVE4_COMPUTE_MP_PM_FUNC_FUNC__MASK			0x000ffff0
+#define NVE4_COMPUTE_MP_PM_FUNC_FUNC__SHIFT			4
+
+#define NVE4_COMPUTE_MP_PM_UNK33DC				0x000033dc
+
 #define NVE4_COMPUTE_LAUNCH_DESC__SIZE				0x00000100
 #define NVE4_COMPUTE_LAUNCH_DESC_6				0x00000018
 #define NVE4_COMPUTE_LAUNCH_DESC_6_NOTIFY__MASK			0x00000c00