nvc0: add support for linear and buffer textures and RTs

1 files changed, 32 insertions, 9 deletions

diff --git a/src/gallium/drivers/nvc0/nvc0_tex.c b/src/gallium/drivers/nvc0/nvc0_tex.c
index a4573d7dbf4..0a1bc379868 100644
--- a/src/gallium/drivers/nvc0/nvc0_tex.c
+++ b/src/gallium/drivers/nvc0/nvc0_tex.c
@@ -60,7 +60,7 @@ nvc0_create_sampler_view(struct pipe_context *pipe,
    uint32_t swz[4];
    uint32_t depth;
    struct nv50_tic_entry *view;
-   struct nv50_miptree *mt = nv50_miptree(texture);
+   struct nv50_miptree *mt;
    boolean tex_int;
 
    view = MALLOC_STRUCT(nv50_tic_entry);
@@ -104,6 +104,32 @@ nvc0_create_sampler_view(struct pipe_context *pipe,
    if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
       tic[2] |= NV50_TIC_2_COLORSPACE_SRGB;
 
+   /* check for linear storage type */
+   if (unlikely(!nouveau_bo_tile_layout(nv04_resource(texture)->bo))) {
+      if (texture->target == PIPE_BUFFER) {
+         tic[2] |= NV50_TIC_2_LINEAR | NV50_TIC_2_TARGET_BUFFER;
+         tic[1] = /* address offset */
+            view->pipe.u.buf.first_element * desc->block.bits / 8;
+         tic[3] = 0;
+         tic[4] = /* width */
+            view->pipe.u.buf.last_element - view->pipe.u.buf.first_element + 1;
+	 tic[5] = 0;
+      } else {
+         mt = nv50_miptree(texture);
+         /* must be 2D texture without mip maps */
+         tic[2] |= NV50_TIC_2_LINEAR | NV50_TIC_2_TARGET_RECT;
+         if (texture->target != PIPE_TEXTURE_RECT)
+            tic[2] |= NV50_TIC_2_NORMALIZED_COORDS;
+         tic[3] = mt->level[0].pitch;
+         tic[4] = mt->base.base.width0;
+         tic[5] = (1 << 16) | mt->base.base.height0;
+      }
+      tic[6] =
+      tic[7] = 0;
+      return &view->pipe;
+   }
+   mt = nv50_miptree(texture);
+
    if (mt->base.base.target != PIPE_TEXTURE_RECT)
       tic[2] |= NV50_TIC_2_NORMALIZED_COORDS;
 
@@ -147,9 +173,6 @@ nvc0_create_sampler_view(struct pipe_context *pipe,
    case PIPE_TEXTURE_2D_ARRAY:
       tic[2] |= NV50_TIC_2_TARGET_2D_ARRAY;
       break;
-   case PIPE_BUFFER:
-      tic[2] |= NV50_TIC_2_TARGET_BUFFER | NV50_TIC_2_LINEAR;
-      break;
    default:
       NOUVEAU_ERR("invalid texture target: %d\n", mt->base.base.target);
       return FALSE;
@@ -196,10 +219,10 @@ nvc0_validate_tic(struct nvc0_context *nvc0, int s)
          OUT_RING  (chan, (i << 1) | 0);
          continue;
       }
-      res = &nv50_miptree(tic->pipe.texture)->base;
+      res = nv04_resource(tic->pipe.texture);
 
       if (tic->id < 0) {
-         uint32_t offset = tic->tic[1];
+         uint32_t offset = res->offset + tic->tic[1];
 
          tic->id = nvc0_screen_tic_alloc(nvc0->screen, tic);
 
@@ -214,8 +237,8 @@ nvc0_validate_tic(struct nvc0_context *nvc0, int s)
          OUT_RING  (chan, 0x100111);
          BEGIN_RING_NI(chan, RING_MF(DATA), 8);
          OUT_RING  (chan, tic->tic[0]);
-         OUT_RELOCl(chan, res->bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
-         OUT_RELOC (chan, res->bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
+         OUT_RELOCl(chan, res->bo, offset, res->domain | NOUVEAU_BO_RD);
+         OUT_RELOC (chan, res->bo, offset, res->domain | NOUVEAU_BO_RD |
                     NOUVEAU_BO_HIGH | NOUVEAU_BO_OR, tic->tic[2], tic->tic[2]);
          OUT_RINGp (chan, &tic->tic[3], 5);
 
@@ -231,7 +254,7 @@ nvc0_validate_tic(struct nvc0_context *nvc0, int s)
       res->status |=  NOUVEAU_BUFFER_STATUS_GPU_READING;
 
       nvc0_bufctx_add_resident(nvc0, NVC0_BUFCTX_TEXTURES, res,
-                               NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
+                               res->domain | NOUVEAU_BO_RD);
 
       BEGIN_RING(chan, RING_3D(BIND_TIC(s)), 1);
       OUT_RING  (chan, (tic->id << 9) | (i << 1) | 1);