summaryrefslogtreecommitdiffstats
path: root/src/gallium/drivers/nv50
diff options
context:
space:
mode:
authorEric Anholt <[email protected]>2012-07-18 22:58:15 -0700
committerEric Anholt <[email protected]>2012-07-20 11:05:39 -0700
commitb2a44cde6468fb6065169194fe3a67b2f4738b71 (patch)
tree3a94a35a6a1e60a0bad608b8c6787aafcb9ac986 /src/gallium/drivers/nv50
parent8ab5842a6d992956ee365c0e0232c6e6b907863e (diff)
i965/gen7: Increase the WM threads to hardware limits.
This thread count is only supposed to be enabled when "WIZ Hashing Disable in GT_MODE register enabled." I've always been confused whether that means the bit in the register should be 1 or 0. For my IVB GT2's register 0x7008 value of 0x0, this appears to work fine. Improves l4d2 performance at 640x480 by 0.88 +/- 0.11% (n=88). Improves performance with rasterization at 1280x1024 by 1.45% +/- 0.36% (n=6). Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/gallium/drivers/nv50')
0 files changed, 0 insertions, 0 deletions